• ETRI Journal
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• v.29 no.4
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• pp.530-532
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• 2007

This paper presents a simple method to implement a complete on-line portable wireless holter including an electrocardiogram (ECG) monitoring, processing, and communication protocol. The proposed algorithm significantly reduces the hardware resources of threshold estimation for ECG compression, using the standard deviation updated with each new input signal sample. The new method achieves superior performance in terms of hardware complexity, channel occupation and memory requirements, while keeping the ECG quality at a clinically acceptable level.

• Korean Journal of Remote Sensing
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• v.8 no.1
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• pp.59-69
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• 1992

The IMAPRO sotfware package was mainly focused to provide an algorithm which is capable of displaying various color composite images on IBM PC, VGA(Video Graphic Array) card with no special hardware. It displays the false color images using a low-cost eight-bit place refresh buffer. This produces similar quality to the one obtained from image board with three eight-bit plane. Also, it provides user friendly menu driven method for the user who are not familier with technical knowladge of image processing. It may prove useful for universities, institute and private company where expensive hardware is not available.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.225-233
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• 2004

A novel real-time color gamut mapping method is described. The color gamut mapping method that is used for enhancing the color reproduction quality between PC monitor and printer devices is adopted for digital TV display quality enhancement. The high definition digital TV display devices operate at the clock speed of around 70MHz ～ 150MHz and permit several nano seconds for real-time gamut mapping. Thus, the concept of three-dimensional reduced resolution look-up table is introduced for real-time processing. The required hardware can be greatly reduced by look-up table resolution adjustment. The proposed hardware architecture is successfully implemented in FPGA and ASIC and also successfully adopted in digital TV display quality enhancement purposes.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.1071-1074
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• 2002

In this paper, power quality analysis system is proposed where voltage or current waveforms are nonsinusoidal. The proposed system relies on the FFT algorithm to compute real and reactive power. The advantage of system is that harmonic analysis is carried out on a period of the input signal. The proposed system is based on FFT processor which is designed using VHDL(Very high-speed integrated circuit Hardware Description Language). In the design of FFT processor, radix- $2^2$ is adopted to reduce several complex multipliers for twiddle factor. Complex multiplier is implemented as only shifters and adders. Therefore, the system is able to have both high hardware efficiency and high performance.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.814-817
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• 2007

We present a hybrid hardware architecture capable of encoding and decoding a full HD resolution video with 60 fps. A number of technical modifications are applied to an existing image compression algorithm not only to accommodate large videos at a high frame rate but to enhance the quality of synthetic images, such as characters and video game images. Image quality of the proposed algorithm at a 1/6 compression ratio was comparable to that of the BTC based 1/3 compression algorithm.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.6
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• pp.1463-1479
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• 2013

In this paper, we propose an unequal protection physical coding sub-layer (PCS) forward error correction (FEC) scheme for efficient and high-quality transmission of video data over optical access networks. Through identifying and resolving the unequal importance of different video frames and passing this importance information from MAC-layer to PCS, FEC scheme of PCS can be adaptive to application-layer data. Meanwhile, we jointly consider the different channel situations of optical network unit (ONU) and improve the efficiency of FEC redundancy by channel adaptation. We develop a theoretical algorithm and a hardware method to achieve efficient FEC assignment for the proposed unequal protection scheme. The theoretical FEC assignment algorithm is to obtain the optimal FEC redundancy allocation vector that results in the optimum performance index, namely frame error rate, based on the identified differential importance and channel situations. The hardware method aims at providing a realistic technical path with negligible hardware cost increment compared with the traditional FEC scheme. From the simulation results, the proposed Channel and Application-layer data Adaptation Unequal Protection (CAAUP) FEC scheme along with the FEC ratio assignment algorithm and the hardware method illustrates the ability of efficient and high-quality transmission of video data against the random errors in the channel of optical access networks.

• 한국HCI학회:학술대회논문집
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• 2008.02a
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• pp.414-419
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• 2008

3D rendering is a critical process for a movie production, advertisement, interior simulation, medical and many other fields. Recently, several effective rendering methods have been developed for the photo-realistic image generation. With a rapid performance enhancement of graphics hardware, physically based 3D rendering algorithm can now often be approximated in real-time games. However, the high quality of global illumination, required for the image generation in the 3D animation production community is a still very expensive process. In this paper, we propose a new rendering method to create photo-realistic global illumination effect efficiently by harnessing the high power of the recent GPUs. Final gathering routines in our global illumination module are accelerated by programmable graphics hardware. We also simulate physically based light transport on a ray tracing based rendering algorithm with photon mapping effectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.379-385
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• 2015

This paper proposes the hardware architecture of high performance ALF(Adaptive Loop Filter) for efficient filter coefficient estimation. In order to make the original image which has high resolution and high quality into highly compressed image effectively and also, subjective image quality into improved image, the ALF technique of HEVC performs a filtering by estimating filter coefficients using statistical characteristics of image. The proposed ALF hardware architecture is designed with a 2-step pipelined architecture for a reduction in performance cycle by analysing an operation relationship of Cholesky decomposition for the filter coefficient estimation. Also, in the operation process of the Cholesky decomposition, a square root operation is designed to reduce logic area, computation time and computation complexity by using the multiplexer, subtracter and comparator. The proposed hardware architecture is designed using Xilinx ISE 14.3 Vertex-7 XC7VCX485T FPGA device and can support 4K UHD@40fps in real time at a maximum operation frequency of 186MHz.

• Proceedings of the KSR Conference
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• 2004.06a
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• pp.837-841
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• 2004

In order to improve the speed of railway, several parameters and/or technical issues, which are affecting speed improvement negatively, need to be considered in addition to the enhancement of physical performance of the railway system such as maximum speed, speed at curve, and speed at turnout track. The parameters under complicated situation of railway system are from the areas of rolling stocks, track, power system, signalling, etc. In general, two different aspects of technical issues can be evaluated; Technical issues in the hardware aspect and technical issues in the software aspect. The hardware parameters include running performance, braking performance, and power performance, while the software factors are rules, regulations, and riding quality. In this investigation, a comparison study between hardware and software aspects in technical issues was conducted to provide technical information on the amendment of railway speed-up regulations.

• Transactions on Electrical and Electronic Materials
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• v.18 no.6
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• pp.320-322
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• 2017

In this paper, a high-performance, low-area gradient-magnitude calculator architecture is proposed, based on approximate image processing. To reduce the computational complexity of the gradient-magnitude calculation, vector properties, the symmetry axis, and common terms were applied in a hardware-resource-shared architec-ture. The proposed gradient-magnitude calculator was implemented using an Altera Cyclone IV FPGA (EP4CE115F29) and the Quartus II v.16 device software. It satisfied the output-data quality while reducing the logic elements by 23% and the embedded multipliers by 76%, compared with previous work.