• Journal of Information Processing Systems
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• 제5권4호
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• pp.187-196
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• 2009

This paper presents compact cryptographic hardware architecture suitable for the Mobile Trusted Module (MTM) that requires low-area and low-power characteristics. The built-in cryptographic engine in the MTM is one of the most important circuit blocks and contributes to the performance of the whole platform because it is used as the key primitive supporting digital signature, platform integrity and command authentication. Unlike personal computers, mobile platforms have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for a compact cryptographic hardware module are required. The proposed cryptographic hardware has a chip area of 38K gates for RSA and 12.4K gates for unified SHA-1 and SHA-256 respectively on a 0.25um CMOS process. The current consumption of the proposed cryptographic hardware consumes at most 3.96mA for RSA and 2.16mA for SHA computations under the 25MHz.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제12권2호
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• pp.829-842
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• 2018

Unmanned Aerial Vehicle (UAV) is diversely utilized in our lives such as daily hobbies, specialized video image taking and disaster prevention activities. New ways of UAV application have been explored recently such as UAV-based delivery. However, most UAV systems are being utilized in a passive form such as real-time video image monitoring, filmed image ground analysis and storage. For more proactive UAV utilization, there should be higher-performance UAV and large-capacity memory than those presently utilized. Against this backdrop, this study described the general matters on proactive software platform and high-performance UAV hardware for real-time target tracking; implemented research on its design and implementation, and described its implementation method. Moreover, in its established platform, this study measured and analyzed the core-specific CPU consumption.

• 대한임베디드공학회논문지
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• 제16권6호
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• pp.313-321
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• 2021

The global market for medical devices is huge, and it will continue showing remarkable growth in the future. However, due to the entry barrier to develop medical devices, many domestic companies have technical problems in entering the medical device industry. In this paper, we introduce an open platform that can help with research and development for companies in the healthcare industry. This open platform consists of a hardware part and a software part. A hardware part is combined into CPU, base and other modules that are easy to replace and assemble. A software part is based on application software for development developed by Bionet. We test the performance of the open medical device platform using a biosignal processing algorithm.

• 한국정보통신학회논문지
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• 제24권12호
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• pp.1688-1696
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• 2020

기존 클라우드 기반 Internet-of-Things(IoT) 시스템의 네트워크 정체와 서버 과부하로 인한 지연, 데이터 이동으로 인한 보안 및 프라이버시 이슈를 해결하기 위하여 엣지 기반의 IoT 시스템으로 IoT의 패러다임이 움직이고 있다. 하지만 엣지 기반의 IoT 시스템은 여러 제약으로 인하여 처리 성능과 동작의 유연성이 부족한 치명적인 문제점을 가지고 있다. 처리 성능을 개선하기 위하여 응용 특화 하드웨어를 엣지 디바이스에 구현할 수 있지만, 고정된 기능으로 인하여 특정 응용 이외에는 성능 향상을 보여줄 수 없다. 본 논문은 엣지 디바이스의 제한된 하드웨어 자원에서 다양한 응용 특화 하드웨어를 주문형 부분 재구성을 통해 사용할 수 있고, 이를 통해 엣지 디바이스의 처리 성능과 동작의 유연성을 증가시킬 수 있는 엣지 중심의 Metamorphic IoT(mIoT) 플랫폼을 소개한다. 실험 결과에 따르면, 재구성 알고리즘을 엣지에서 실행하는 엣지 중심의 mIoT 플랫폼은 재구성 알고리즘을 서버에서 실행하는 이전 연구에 비해 엣지의 서버 접근 횟수를 최대 82.2% 줄일 수 있었다.

• 융합신호처리학회논문지
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• 제13권2호
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• pp.83-90
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• 2012

본 논문에서는 NIOS II 임베디드 플랫폼을 기반으로 하는 지능형 영상 감시 시스템을 구현하였다. 지금까지의 입베디 드 기반의 영상 감시 시스템들은 하드웨어의 의존도가 높아 특정한 목적에 제한되는 단점이 있었다. 이러한 한계를 개 선하기 위하여, 필자들은 그 응용의 목적에 따라 폭 넓게 적용 가능한 유연성이 높은 임베디드 플랫폼을 구현하였다. 소프트웨어 중심 프로그래밍 기법의 주요 문제점인 고속 처리를 위하여, 핵심 부분인 하드웨어 플랫폼에서 SOPC형 NIOS II 임베디드 프로세서와 영상처리 알고리즘을 소프트웨어 프로그래밍과 C2H(The Altera NIOS II C-To-Hardware(C2H) Acceleration Compiler) 컴파일러를 사용하는 하드웨어 프로그래밍을 통합하여 시스템의 성능을 향상 시켰다. 그리고 NIOS II 임베디드 프로세서 플랫폼을 중심으로 각각의 디바이스 인터페이스를 통합 관리하는 서버 시스템을 구축하고, 사용자의 접근 효율을 높이기 위해 네트워크상에서 제어하는 기능을 추가하였다.본 시스템을 영상 감시를 위한 지정된 구역에 설치하여 시험하고 그 성능을 평가하였다.

• 한국멀티미디어학회논문지
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• 제19권4호
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• pp.747-755
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• 2016

Automated guided vehicles have been used for a long time to increase work efficiency in the logistics field, but it is difficult to apply to a variety of logistics sites due to either the restricted movement mechanism or expensive devices. In this paper, we present a flexible software architecture that is hardware-independent for a mobile power cart of the follow mode and implement it using a ROS software platform. Through the SCV analysis for the system functionalities, we design a package to track a user movement and a package to control a new hardware platform. It has an advantage to use a variety of movement algorithms and hardware platforms by applying the strategy pattern and the template method pattern for the design of a software architecture. Through the performance evaluation, we show that the proposed design is maintainable in terms of a software complexity and it detects a user's movement by obtaining a user skeleton information so that it can control a hardware platform to move at a certain distance.

• Journal of information and communication convergence engineering
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• 제13권3호
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• pp.145-151
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• 2015

We describe in this paper a hardware-based improvement scheme of a real-time automatic speech recognition (ASR) system with respect to speed by designing a parallel feature extraction algorithm on a Field-Programmable Gate Array (FPGA). A computationally intensive block in the algorithm is identified implemented in hardware logic on the FPGA. One such block is mel-frequency cepstrum coefficient (MFCC) algorithm used for feature extraction process. We demonstrate that the FPGA platform may perform efficient feature extraction computation in the speech recognition system as compared to the generalpurpose CPU including the ARM processor. The Xilinx Zynq-7000 System on Chip (SoC) platform is used for the MFCC implementation. From this implementation described in this paper, we confirmed that the FPGA platform is approximately 500× faster than a sequential CPU implementation and 60× faster than a sequential ARM implementation. We thus verified that a parallelized and optimized MFCC architecture on the FPGA platform may significantly improve the execution time of an ASR system, compared to the CPU and ARM platforms.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2008년도 춘계학술대회 논문집
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• pp.1051-1059
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• 2008

In the development process of an ECU (Electrical Control Unit), numerous tests are necessary to evaluate the performance and control algorithm. The vehicle based test is expensive and requires long time. Also, it is difficult to guarantee the safety of the test driver. To overcome the various problems faced in the development process, the ECU test has been done using HIL (Hardware In the Loop). The HIL environment has the actual hardware including an ECU and a virtual vehicle model. In this paper, the test platform environment is devloped for the AWS ECU black box test. The test platform is built on HIL (Hardware In the Loop) architecture. Using the developed test platform, the control algorithm of the AWS ECU can be evaluated under the virtual driving condition of the bi-modal tram. Driving conditions, such as a front steering angle and vehicle velocity, are defined through the PC (Personal Computer) input. Input signals are transformed to electrical signals in the PC. These signals become the input conditions of the AWS ECU. The AWS ECU is stimulated by arbitory input conditons, and responses of the system are observed.

• Journal of Communications and Networks
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• 제13권1호
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• pp.70-76
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• 2011

This paper presents the unified user equipment (UE) baseband modulation and demodulation (modem) hardware platform architecture to support multiple radio access technologies. In particular, this platform selectively supports two systems; one is HEDGE system, which is the combination of third generation partnership project (3GPP) Release 7 high speed packet access evolution (HSPA+) and global system for mobile communication (GSM)/general packet radio service (GPRS)/enhanced data rates for GSM evolution (EDGE), while the other is LEDGE system, which is the combination of 3GPP Release 8 long term evolution (LTE) and GSM/GPRS/EDGE. This is done by applying the flexible pin multiplexing scheme to a hardwired pin mapping process. On the other hand, to provide stable connection, high portability, and high debugging ability, the stacking structure is employed. Here, a layered board architecture grouped by functional classifications is applied instead of the conventional one flatten board. Based on this proposed configuration, we provide a framework for the verification step in wireless cellular communications. Also, modem function/scenario test and inter-operability test with various base station equipments are verified by system requirements and scenarios.

• 전기전자학회논문지
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• 제17권2호
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• pp.202-207
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• 2013

본 논문은 기존의 FAST와 BRIEF 알고리즘을 Zynq-7000 Soc Platform에서 하드웨어로 구현했다. 대표적으로 SIFT 나 SURF 알고리즘을 사용하여 특징점 기반 하드웨어 가속기로 구현 하지만, 하드웨어 비용과 내부 메모리가 많이 필요하다. 제안하는 FAST & BRIEF 가속기는 기존의 SIFT 나 SURF 가속기 보다 내부 메모리 사용량을 약 57%, 하드웨어 비용을 약 70% 정도 감소하고, 수행 시간은 Clock 당 0.17 Pixel를 처리한다.