• 항공우주기술
• /
• 제11권1호
• /
• pp.145-157
• /
• 2012

상평면상에서 추력기를 사용하는 자세제어 시스템의 리밋 사이클을 해석하는 새로운 기법이 논문에 의해서 제안되었다. 그러나 이것은 소프트 시뮬레이션상에서 Haloulakos 방식보다 제안 방식이 정확함을 보였지만, 실제 시스템으로 검증하지는 못하였다. 그래서 저자의 제안 방식을 KSLV-I 추력기 자세제어 시스템에 대한 실시간 모의시험으로 검증하고, 리밋 사이클 해석에 대하여 실시간 모의시험 결과와 이론적으로 구한 값을 비교/분석하였다.

• 전기전자학회논문지
• /
• 제12권2호
• /
• pp.75-80
• /
• 2008

There are many researches to reduce power consumption of battery-operated Transceiver for 2.4 GHz smartRF applications. However, components such as processor, memory and LCD based power managements reach the limit of reducing power consumption. To overcome the limit, this research proposes novel low-power Transceiver and transceiver Hardware Design. Experimental results in the real smartRF Transceiver show that the proposed methods can reduce power consumption additionally than component based power managements.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제13권5호
• /
• pp.2357-2380
• /
• 2019

In this paper, we investigate the impact of hardware impairments (HWIs) on the performance of a downlink massive MIMO system. We consider a single-cell system with maximum ratio transmission (MRT) as precoding scheme, and with all the HWIs characteristics such as phase noise, distortion noise, and amplified thermal noise. Based on the system model, we derive closed-form expressions for a typical user data rate under two scenarios: when a common local oscillator (CLO) is used at the base station and when separated oscillators (SLOs) are used. We also derive closed-form expressions for the downlink transmit power required for some desired per-user data rate under each scenario. Compared to the conventional system with ideal transceiver hardware, our results show that impairments of hardware make a finite upper limit on the user's downlink channel capacity; and as the number of base station antennas grows large, it is only the hardware impairments at the users that mainly limit the capacity. Our results also show that SLOs configuration provides higher data rate than CLO at the price of higher power consumption. An approach to minimize the effect of the hardware impairments on the system performance is also proposed in the paper. In our approach, we show that by reducing the cell size, the effect of accumulated phase noise during channel estimation time is minimized and hence the user capacity is increased, and the downlink transmit power is decreased.

• 정보보호학회논문지
• /
• 제12권5호
• /
• pp.95-105
• /
• 2002

본 논문에서는 공개키 암호 시스템에서 인증, 키 교환 및 전자 서명을 위해 사용되는 RSA 공개키 암호 알고리즘의 효율적인 하드웨어 구현 방법에 대해 기술하였다. RSA 공개키 알고리즘은 모듈러 멱승 연산에 의해 계산되어지며, 모듈러 멱승 연산은 반복적인 모듈러 곱셈 연산을 필요로 한다. 모듈러 곱셈 구현을 위한 많은 알고리즘 중, 하드웨어 구현의 효율성 때문에 Montgomery 알고리즘이 많이 사용되어지고 있다. 지금까지 몽고메리 알고리즘을 이용하여 고성능의 RSA 암호회로를 설계하는 연구는 많이 수행되어 왔으나, 대부분의 연구가 시스템의 고성능을 위한 연산 시간의 감소에 중점을 두고있다. 하드웨어 구현에 제한이 있는 시스템에서 하드웨어 설계 시 가장 고려해야 할 사항은 시스템의 성능과 면적을 고려한 설계이다. 이러한 이유로, 본 논문에서는 기존의 Montgomery 알고리즘을 저면적 회로에 적합한 구조로 개선하였으며, 개선된 알고리즘을 이용하여 ETRI에서 개발한 스마트 카드용 에뮬레이팅 시스템인 IESA 시스템에 적용하여 검증하였다.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 1996년도 Proceedings of the Korea Automatic Control Conference, 11th (KACC); Pohang, Korea; 24-26 Oct. 1996
• /
• pp.77-82
• /
• 1996

This paper is concerned with how to utilize kinematic redundancy to reconstruct the inverse kinematic solution which is not attainable due to hardware limitations. By analyzing the error due to hardware limitations, we are to show that the recoverability of limitation reduces to the solvability of a reconstruction equation under the feasibility condition. It will be next shown that the reconstruction equation is solvable if the configuration is not a joint-limit singularity. The reconstruction method will be proposed based on the geometrical analysis of recoverability of hardware limitations. The method has the feature that no task motion error is induced by the hardware limitations while minimizing a possible null motion error, under the recoverability assumed.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2003년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
• /
• pp.435-437
• /
• 2003

Recently, as the road capacity reaches the limit and environmental problems becomes serious, there is gradually increased a need for railroad vehicles that are environment-friendly and have time regularity, reliability and safety. Accordingly, in addition to conventional railroad vehicles, lots of vehicles are being newly developed. We developed the hardware and software of the measurement system for on-line test and evaluation of korean hish speed train. The software controls the hardware of the measurement data and acts as interface between users and the system hardware. In this paper, we is studied for electric apparatus performance of railway vehicle using sensor. In order to this test is developed signal conversion system. Using this system, we obtained important result for pantograph voltage, battery voltage, axle speed, and running speed.

• 한국전기전자재료학회논문지
• /
• 제16권12S호
• /
• pp.1210-1216
• /
• 2003

Recently, as the road capacity reaches the limit and environmental problems becomes serious, there is gradually increased a need for railroad vehicles that are environment-friendly and have time regularity, reliability, and safety. Accordingly, in addition to conventional railroad vehicles, lots of vehicles are being newly developed. We developed the hardware and software of the measurement system for on-line test and evaluation of korean high speed train. The software controls the hardware of the measurement system and acts as interface between users and the system hardware. In this paper, practical experiment are performed to verify mechanical performance of motor and main transformer for Korean high speed rail. The experimental test carried out by using new temperature measurement method and verify the temperature performance of motor and transformer is verified.

• IEIE Transactions on Smart Processing and Computing
• /
• 제4권4호
• /
• pp.237-250
• /
• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2002년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
• /
• pp.197-199
• /
• 2002

The invention of VHDL(Very High Speed Integrated Circuit Hardware Description Language), Technical language of Hardware, is a kind of turning point in digital circuit designing, which is being more and more complicated and integrated. Because of its excellency in expression ability of hardware, VHDL is not only used in designing Hardware but also in simulation for verification, and in exchange and conservation, composition of the data of designs, and in many other ways. Especially, It is very important that VHDL is a Technical language of Hardware standardized by IEEE, intenational body with an authority. The biggest problem in modern circuit designing can be pointed out in two way. One is a problem how to process the rapidly being complicated circuit complexity. The other is minimizing the period of designing and manufacturing to survive in a cutthroat competition. To promote the use of VHDL, more than a simple use of simulation by VHDL, it is requested to use VHDL in composing logical circuit with chip manufacturing. And, by developing the quality of designing technique, it can contribute for development in domestic industry related to ASIC designing. In this paper in designing SMPS(Switching mode power supply), programming PWM by VHDL, it can print static voltage by the variable load, connect computer to chip with byteblaster, and download in Max(EPM7064SLCS4 - 5)chip of ALTER. To achieve this, it is supposed to use VHDL in modeling, simulating, compositing logic and product of the FPGA chip. Despite its limit in size and operating speed caused by the specific property of FPGA chip, it can be said that this method should be introduced more aggressively because of its prompt realization after designing.

• 정보과학회 논문지
• /
• 제42권2호
• /
• pp.177-182
• /
• 2015

오늘날에는 코어당 클락 속도 발전이 한계에 부딪히게 되면서 멀티 코어 프로세서의 시대가 도래하였다. 최근에는 서버나 데스크톱 환경뿐만 아니라 모바일 환경까지 널리 보급되고 있다. 이러한 구조에서는 프로세스간 성능 간섭 현상이 발생하게 되는데, 이를 방지하기 위해서 사용되는 캐시 파티셔닝 기법은 소프트웨어적인 방법과 하드웨어적인 방법 크게 두 가지로 나누어진다. 하지만 동적 캐시 파티셔닝시에 소프트웨어 캐시 파티셔닝 기법은 페이지 복사 오버헤드로 인해서 성능 향상을 기대하기 힘든데, 이에 반해서 하드웨어 캐시 파티셔닝은 이러한 페이지 복사에서 자유롭다는 장점이 있다. 이 논문에서는 상용 프로세서 중에서 하드웨어적으로 캐시 파티셔닝 기능을 제공하는 AMD Opteron 프로세서에서 소프트웨어적 캐시 파티셔닝 기법인 페이지 컬러링과 하드웨어 캐시 파티셔닝의 성능을 정적 캐시 파티셔닝 환경에서 비교해봄으로써, 하드웨어 캐시 파티셔닝의 동적 캐시 파티셔닝 활용 가능성 여부를 알아본다.