• Journal of Korean Society of Transportation
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• v.33 no.1
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• pp.70-80
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• 2015

In recent years, tram has been the focus of a new mode of public transportation that can solve traffic jams and decrease public transit usage and environmental problem. This research is in the works to develop a tram signal controller and signal control strategies, and aim to resolve the problem of what could happen if a tram system was installed in general road. We developed the hierarchical signal control strategies to obtain a minimum tram bandwidth and to minimize vehicle delay, in order to perform a priority control to include passive and active signal priority control strategies. The strategies was produced for S/W and H/W, it is based in standard traffic signal controller. We conducted a micro simulation test to evaluate the hierarchical signal control strategies, which showed that the developed optimization model is effective to prevent a tram's stop in intersection, to reduce a tram's travel time and vehicle's delay.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.4
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• pp.825-840
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• 2015

Adaptive bitrate (ABR) streaming technology has become an important and prevalent feature in many multimedia delivery systems, with content providers such as Netflix and Amazon using ABR streaming to increase bandwidth efficiency and provide the maximum user experience when channel conditions are not ideal. Where such systems could see improvement is in the delivery of live video with a closed loop cognitive control of video encoding. In this paper, we present streaming camera system which provides spatially and temporally adaptive video streams, learning the user's preferences in order to make intelligent scaling decisions. The system employs a hardware based H.264/AVC encoder for video compression. The encoding parameters can be configured by the user or by the cognitive system on behalf of the user when the bandwidth changes. A cognitive video client developed in this study learns the user's preferences(i.e. video size over frame rate) over time and intelligently adapts encoding parameters when the channel conditions change. It has been demonstrated that the cognitive decision system developed has the ability to control video bandwidth by altering the spatial and temporal resolution, as well as the ability to make scaling decisions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.61-70
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• 2016

This paper describes a new PMU(parametric measurement unit) design technique for automatic test equipment(ATE). Only one DDA(differential difference amplifier) is used to force the test signals to DUT(device under test), while conventional design uses two or more amplifiers to force test signals. Since the proposed technique does not need extra amplifiers in feedback path, the proposed PMU inherently guarantees stable operation. Moreover, to measure the response signals from DUT, proposed technique also adopted only one DDA amplifier as an IA(instrument amplifier), while conventional IA uses 3 amplifiers and several resistors. The DDA adopted two rail-to-rail differential input stages to handle full-range differential signals. Gain enhancement technique is used in folded-cascode type DDA to get open loop gain of 100 dB. Proposed PMU design enables accurate and stable operation with smaller hardware and lower power consumption. This PMU is implemented with 0.18 um CMOS process and supply voltage is 1.8 V. Input ranges for each force mode are 0.25~1.55 V at voltage force and 0.9~0.935 V at current force mode.