• Nuclear Engineering and Technology
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• v.29 no.2
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• pp.167-174
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• 1997

The method that the operating condition of Control Rod Drive Mechanism (CRDM) can be monitored without mounting sensors within CRDM housing was developed, and by using this developed method the closed-loop controller for the CRDM was designed which can optimize the performance and maximize the reliability of CRDM operation. Neural network is utilized as pattern recognition engine in detecting CRDM actuation. In this paper, most problems in previous open loop system are resolved. The control algorithms for closed-loop system ore developed and implemented within the hardware of timing controller based on microprocessor. All functions in the timing controller ore verified by means of real time CRDM simulator. The results show that the timing controller performs its intended functions properly.

• 전자공학회논문지 IE
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• v.49 no.2
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• pp.30-39
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• 2012

An effective drowsy driver detection system is needed, because the probability of accident is high for drowsy driving and its severity is high at the time of accident. However, the drowsy driver detection system that uses bio-signals or vision is difficult to be utilized due to high cost. Thus, this paper proposes a drowsy driver detection algorithm by using steering angle sensor, which is attached to the most of vehicles at no additional cost, and vehicle information such as brake switch, throttle position signal, and vehicle speed. The proposed algorithm is based on jerk criterion, which is one of drowsy driver's steering patterns. In this paper, threshold value of each variable is presented and the proposed algorithm is evaluated by using acquired vehicle data from hardware in the loop simulation (HILS) through CAN communication and MATLAB program.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.117-120
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• 2002

In this paper, we construct cryptographic accelerators using hardware Implementations of HMACS based on a hash algorithm such as MD5.It is basically a secure version of his previous algorithm, MD4 which is a little faster than MD5 The algorithm takes as Input a message of arbitrary length and produces as output a 128-blt message digest The input is processed In 512-bit blocks In this paper, new architectures, Iterative and full loop, of MD5 have been implemented using Field Programmable Gate Arrays(FPGAS). For the full-loop design, the performance Is about 500Mbps @ 100MHz

• ETRI Journal
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• v.28 no.3
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• pp.275-281
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• 2006

A very simple and efficient scheme for jitter reduction is proposed for a carrier frequency recovery loop using phase differential frequency estimation, which estimates the current frequency offset based on the difference of the average phases of two successive intervals. Analytical and numerical results presented in this paper show that by simply overlapping the observation intervals by half for frequency offset estimations, both the steady-state and transient performances can be improved. The proposed scheme does not require any additional hardware circuitry, but results in improved performance even with reduced complexity.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.39-46
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• 1999

In this paper, we propose new hardware architecture of a fast searcher for an initial code acquisition in wideband CDMA wireless local loop systems. The proposed searcher uses double-dwell serial search algorithm and has N active correlators for the high performance code acquisition. Since the N active correlators are designed with pipelined architecture, it is possible to reduce the hardware complexity with only one energy calculation. Our architecture is designed using VHDL to meet wideband CDMA wireless local loop standard and verified under JTC wideband channels. Average code acquisition time of the proposed fast searcher which has 16 correlators is about 40 seconds in case of initial installation and 0.16 seconds when a base station is known. The verified fast searcher is synthesized with in $0.6\mu\textrm{m}$ LG library. The synthesized searcher has 15.8K rates when the number of 4he correlators is 16.

• Journal of Advanced Marine Engineering and Technology
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• v.37 no.6
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• pp.582-588
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• 2013

Solid Oxide Fuel Cell (SOFC) has been focused as a promising power source, which can replace a diesel engine regarding as major source of air pollution by the ship, due to high efficiency and eco-friendly. High operating temperature of SOFC is enable to secure of high efficiency, use various fuels and no need of high priced catalyst, but it may damage to components of SOFC. Therefore temperature control system has to be designed and validated before employing the fuel cell system for securing high efficiency and reliability. In this paper, instead of using typical method to validate performance of the controller, which consumes high cost and time, performance validation system using Hardware-in-the-loop simulation was developed and validated performence of the designed temperature controller for SOFC system.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.165-171
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• 1996

A noncoherent full-digital PN(pseudo noise) code acquisition/tracking loop has been presetned and implemented in FPGA for the CDMA band-limited direct-sequence spread-spectrum (DS-SS) signals. It employs a simple decimator to control of local PN code phase to lower the hardware cost, and a second order loop to enable the more accurate tracking. The proposed acquisition/tracking loop has been designed in RTL-level VHDL, synthesized into logic gates using the design analyzer of synopsys software, implemented in an ALTERA FPGA chip, and tested. The number of logic gates used in the implemented FPGA chip is around 7000. The functionality has been verified using a PC interface circuitry and a logic analyzer.

• Journal of Energy Engineering
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• v.25 no.1
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• pp.113-121
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• 2016

Polymer electrolyte membrane fuel cell(PEMFC) requires cooling system to maintain the proper operating temperature(about $65^{\circ}C{\sim}75^{\circ}C$) because the efficiency and power are affected by operating temperature. In order to retain the operating temperature of PEMFC, cooling system and coolant control logic are needed. Hardware-in-the-loop simulation(HILS) is one of effective methods to study and evaluate control algorithm. In this paper, the HILS system was designed to study the coolant control algorithm. The models of HILS system consisted of PEMFC, heat exchanger, and external environment associated with temperature. The hardwares in HILS system are 3-way valves, pumps, and a heat exchanger. The priority control and the control target temperature were investigated to improve the control performance using HILS. The 3-way valve in $1^{st}$ cooling circuit was selected as priority control target. The under limit value of $2^{nd}$ 3-way valve set as a function of PEMFC power and $2^{nd}$ circuit coolant temperature to correct temperature control performance. As a result, the temperature of PEMFC is stably controlled.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2659-2661
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• 2002

The development of guided missile requires complex guidance schemes and hardware units because of high maneuver, delicate and variable missions. In this point of view, simulation systems and facilities which test missile hardwares and softwares are needed. This paper introduces the hardware-in-the loop simulation system and facilities which include the real-time computation systems and 3 Axis FMS(Flight Motion Simulator).

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.522-527
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• 1987

This paper describes the hardware of analog-to-digital converter to process the rate output of analog servo loop for the gyro rebalance of INS. The analog-to-digital converter is designed by voltage-to-frequency method which is generally used in INS, and this scheme fits well into the strapdown INS that requires the wide dynamic range and linearity. The output of the designed voltage to frequency converter is tested by computer through the counter and all the factors which affect the performance are considered.