• ETRI Journal
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• v.30 no.5
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• pp.707-717
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• 2008

This paper presents two types of high-speed hardware architectures for the block cipher ARIA. First, the loop architectures for feedback modes are presented. Area-throughput trade-offs are evaluated depending on the S-box implementation by using look-up tables or combinational logic which involves composite field arithmetic. The sub-pipelined architectures for non-feedback modes are also described. With loop unrolling, inner and outer round pipelining techniques, and S-box implementation using composite field arithmetic over $GF(2^4)^2$, throughputs of 16 Gbps to 43 Gbps are achievable in a 0.25 ${\mu}m$ CMOS technology. This is the first sub-pipelined architecture of ARIA for high throughput to date.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1714-1719
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• 2003

Antilock Brake System (ABS) is indispensable safety equipment for vehicles today. In order to develop new ABS ECU suitable for pneumatic brake system of a bus, a Hardware In-the-Loop Simulation (HILS) System was developed. In this HILS, the pneumatic brake system of a bus and antilock brake component were used as hardware. For the computer simulation, the 14-Degree of Freedom (DOF) bus dynamic model was constructed using the Matlab/Simulink software package. This model was compiled and downloaded in the simulation board, where the Power PC processor was used for real-time simulation. Additional commercial package, the ControlDesk was used to monitor the dynamic simulation results and physical signal values. This paper will focus on the procedure and results of evaluating the ECU in the HILS simulation. Two representative cases, wet basalt road and $split-{\mu}$ road, were used to simulate real road conditions. At each simulated road, the vehicle was driven and stopped under the help of the developed ECU. In each simulation, the dynamical behavior of the vehicle was monitored. After enough tests in the laboratory using HILS, the parameter-tuned ECU was equipped in a real bus, which was driven and stopped in the real test field in Korea. And finally, the experiment results of ABS equipped vehicle's dynamic behavior both in HILS test and in test fields were compared.

• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.62-64
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• 2018

In two-stage single-phase inverters, inherent double line frequency component is present at both input and output of the front-end converter. Generally large electrolytic capacitors are required to eliminate the ripple. It is well known that the low frequency ripple shortens the lifespan of the capacitor hence the system reliability. However, the ripple can hardly be eliminated without the hardware combined with an energy storage device or a certain control algorithm. In this paper, a novel power-decoupling control method is proposed to eliminate the double line frequency ripple at the front-end converter of the DC/AC power conversion system. The proposed control algorithm is composed of two loop, ripple rejection loop and average voltage control loop and no extra hardware is required. In addition, it does not require any information from the phase-locked-loop (PLL) of the inverter and hence it is independent of the inverter control. In order to prove the validity and feasibility of the proposed algorithm a 5kW Dual Active Bridge DC/DC converter and a single-phase inverter are implemented, and experimental results are presented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

• International Journal of Aeronautical and Space Sciences
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• v.11 no.4
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• pp.338-344
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• 2010

This paper discusses the development of the control system of a mini quadrotor in Konkuk University for indoor applications. The attitude control system consists of a stability augmentation system, which acts as the inner loop control, and a modern control approach based on modeling will be implemented as the outer loop. The inner loop control was experimentally satisfied by a proportional-derivative controller; this was used to support the flight test in order to validate the modeling. This paper introduces the mathematical model for the simulation and design of the optimal control on the outer loop control. To perform the experimental tests, basic electronic hardware was developed using simple configurations; a microcontroller used as the embedded controller, a low-cost 100 Hz inertial sensors used for the inertial sensing, infra-red sensors were employed for horizontal ranging, an ultrasonic sensor was used for ground ranging and a high performance propeller system built on an quadrotor airframe was also employed. The results acquired from this compilation of hardware produced an automatic hovering ability of the system with ground control system support for the monitoring and fail-safe system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.379-385
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• 2015

This paper proposes the hardware architecture of high performance ALF(Adaptive Loop Filter) for efficient filter coefficient estimation. In order to make the original image which has high resolution and high quality into highly compressed image effectively and also, subjective image quality into improved image, the ALF technique of HEVC performs a filtering by estimating filter coefficients using statistical characteristics of image. The proposed ALF hardware architecture is designed with a 2-step pipelined architecture for a reduction in performance cycle by analysing an operation relationship of Cholesky decomposition for the filter coefficient estimation. Also, in the operation process of the Cholesky decomposition, a square root operation is designed to reduce logic area, computation time and computation complexity by using the multiplexer, subtracter and comparator. The proposed hardware architecture is designed using Xilinx ISE 14.3 Vertex-7 XC7VCX485T FPGA device and can support 4K UHD@40fps in real time at a maximum operation frequency of 186MHz.

• Transactions of the Korean hydrogen and new energy society
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• v.23 no.4
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• pp.323-329
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• 2012

A thermal management system of a proton exchange membrane fuel cell is taken charge of controlling the temperature of fuel cell stack by rejection of electrochemically reacted heat. Two major components of thermal management system are heat exchanger and pump which determines required amount of heat. Since the performance and durability of PEMFC system is sensitive to the operating temperature and temperature distribution inside the stack, it is necessary to control the thermal management system properly under guidance of operating strategy. The control study of the thermal management system is able to be boosted up with hardware in the loop simulation which directly connects the plant simulation with real hardware components. In this study, the plant simulation of fuel cell stack has been developed and the simulation model is connected with virtual data acquisition system. And HIL simulator has been developed to control the coolant supply system for the study of PEMFC thermal management system. The virtual data acquisition system and the HIL simulator are developed under LabVIEWTM Platform and the Simulation interface toolkit integrates the fuel cell plant simulator with the virtual DAQ display and HIL simulator.

• Transactions of the Korean hydrogen and new energy society
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• v.25 no.4
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• pp.405-418
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• 2014

Fuel cells are suitable for a power plant of a unmanned aerial vehicle (UAV) as it is not only environmentally friendly and quiet but also more efficient than an internal combustion engine. A fuel cell hybrid UAV has better performance in endurance than a fuel cell only or battery only UAV. One of the key purposes of making fuel cell hybrid UAVs is having long endurance and now maximum 26 hours of flight is possible. Because optimal design and control methods for fuel cell hybrid UAVs are absolutely needed for their long endurance we have to check the methods. The aircraft made by using application-integrated design method has less BOP mass and better performances. The optimal design and control methods are generally based on computer simulations or Hardware-In-The-Loop simulations by using dynamic models for their design and control. The Hardware-In-The-Loop simulation (HILS) is to use a hardware device like a fuel cell stack as well as a simulation program and it allows for making optimally designed applications. This paper introduce efficient methods of design, control and evaluation for the fuel cell hybrid UAVs.

• KIPE Magazine
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• v.18 no.6
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• pp.48-51
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• 2013

• KIPE Magazine
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• v.23 no.6
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• pp.51-57
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• 2018