• Journal of Power Electronics
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• 제6권2호
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• pp.114-120
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• 2006

This paper compares two types of direct torque controllers for permanent magnet synchronous motors(PMSMs). These controllers both use a single-chip FPGA(Field Programmable Gate Array) but have differing hardware configurations. One of the controllers was constructed by programming a soft-core CPU and hardware logic circuits written in VHDL(Very high speed IC Hardware Description Language), while the other was constructed of only hardware logic circuits. The characteristics of these two controllers were compared in this paper. The results show the controller constructed of only hardware logic circuits was able to shorten the control period and it was able to suppress the low torque ripple.

• 전기학회논문지
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• 제63권4호
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• pp.476-483
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• 2014

This paper describes the operational analysis results of the bipolar DC distribution system coupled with the distributed generators. The energy management for AC/DC power trade and the operational principle of distributed generators and energy storages were first analyzed by computer simulation with PSCAD/EMTDC software. After then a hardware simulator for the bipolar DC distribution system was built, which is composed of the grid-tied three-level inverter, battery storage, super-capacitor storage, and the voltage balancer. Various experiments with the hardware simulator were carried out to verify the operation of bipolar DC distribution system. The developed simulator has an upper-level controller which operates in connection with the controllers for each distributed generator and the battery energy storage based on CAN communication. The developed hardware simulator are possible to use in designing the bipolar DC distribution system and analyzing its performance experimentally.

• 전기학회논문지
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• 제63권8호
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• pp.1046-1054
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• 2014

In this paper, a hardware prototype for the 10kVA 11-level MMC was built and various experimental works were conducted to verify the operation algorithms of MMC. The hardware prototype was designed using computer simulation with PSCAD/EMTDC software. After manufactured in the lab, the hardware prototype was tested to verify the modulation algorithms to form the output voltage, the balancing algorithm to equalize the sub-module capacitor voltage, and the redundancy operation algorithm to improve the system reliability. The developed hardware prototype can be utilized for analyzing the basic operation and performance improvement of MMC according to the modulation and redundancy operation scheme. It also can be utilize to analyze the basic operational characteristics of HVDC system based on MMC.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제16권8호
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• pp.2816-2830
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• 2022

Number Theoretic Transform (NTT) is a method to design efficient multiplier for large integer multiplication, which is widely used in cryptography and scientific computation. On top of that, it has also received wide attention from the research community to design efficient hardware architecture for large size RSA, fully homomorphic encryption, and lattice-based cryptography. Existing NTT hardware architecture reported in the literature are mainly designed based on radix-2 NTT, due to its small area consumption. However, NTT with larger radix (e.g., radix-4) may achieve faster speed performance in the expense of larger hardware resources. In this paper, we present the performance evaluation on NTT architecture in terms of hardware resource consumption and the latency, based on the proposed radix-2 and radix-4 technique. Our experimental results show that the 16-point radix-4 architecture is 2× faster than radix-2 architecture in expense of approximately 4× additional hardware. The proposed architecture can be extended to support the large integer multiplication in cryptography applications (e.g., RSA). The experimental results show that the proposed 3072-bit multiplier outperformed the best 3k-multiplier from Chen et al. [16] by 3.06%, but it also costs about 40% more LUTs and 77.8% more DSPs resources.

• Journal of Advanced Marine Engineering and Technology
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• 제40권6호
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• pp.542-547
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• 2016

최근 사물인터넷의 큰 주목을 받으며 다양한 분야에서 사물 인터넷 응용 서비스에 대한 요구가 증가하고 있다. 사물을 구성하는 핵심으로 오픈소스 하드웨어가 활용되면서 소프트웨어에서 주목받고 있는 '오픈소스'(open-source) 개념이 사물인터넷 시장의 활성화로 하드웨어 분야에서도 큰 주목을 받고 있다. 저렴한 하드웨어 비용과 빠른 개발속도가 장점인 오픈소스 하드웨어의 등장은 사물인터넷 응용 서비스의 아이디어를 구체화할 수 있게 하였다. 본 논문에서는 오픈소스 시스템을 활용하여 주변의 환경 정보를 수집 및 교환하고 처리하는 사물인터넷 응용 서비스 시스템을 구축한다. 전체적인 시스템 구조 및 하드웨어, 소프트웨어 구성을 설명한다.

• 한국정보통신학회논문지
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• 제21권9호
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• pp.1681-1688
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• 2017

본 논문에서는 FPGA와 Nor-Flash를 사용하여 컬러 라인 스캔 카메라를 위한 고속 신호처리 하드웨어 시스템을 구현하였다. 기존의 시스템에서는 소프트웨어를 기반으로 한 고속 DSP가 적용되어 왔고 주로 RGB 개별 논리에 의해 결함을 검출하는 방법이었지만 본 논문에서는 RGB-HSL 변환기, FIFO, HSL 풀-컬러 결함 디코더 및 이미지 프레임 버퍼로 구성된 하드웨어 기반의 결함 검출기를 제안하였다. 결함 검출기는 RGB에서 HSL로의 색상 공간 변환을 위한 하드웨어 기반 룩업테이블과 4K HSL 풀-컬러 결함 디코더로 구성되어 있다. 또한 단일 라인 데이터 기반의 로컬 픽셀 처리 대신 2차원 배열 구조의 이미지 단위 처리를 위해 라인 데이터 축적용 이미지 프레임을 포함한다. 설계된 시스템을 기존의 곡물 선별기에 적용하여 땅콩을 대상으로 선별해 본 결과 효과적임을 알 수 있었다.

• 한국경영과학회:학술대회논문집
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• 대한산업공학회/한국경영과학회 2006년도 춘계공동학술대회 논문집
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• pp.1329-1333
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• 2006

This paper proposes a framework for product development including hardware and software components. The framework provides separation of the hardware dependent software, an integrated product development process, and integration of software components with product configurations and product structures. In order to separates the hardware dependent software, the framework considers product configuration modules and engineering changes of associated hardware and software components. The proposed product development process integrates development of the hardware dependent software into the existing product development process. In order to integrates the hardware dependent software with product configurations and product structures, the framework represents software components by existing product data models in Product Data Management (PDM). The framework is applied to development of a robot system including hardware and software components in order to show its effectiveness.

• Journal of Power Electronics
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• 제13권2호
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• pp.313-321
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• 2013

This paper describes the operation analysis results of a communication-based DC micro-grid using a hardware simulator developed in the lab. The developed hardware simulator is composed of distributed generation devices such as wind power, photovoltaic power and fuel cells, and energy storage devices such as super-capacitors and batteries. Whole system monitoring and control was implemented using a personal computer. The power management scheme was implemented in a main controller based on a TMS320F28335 chip. The main controller is connected with the local controller in each of the distributed generator and energy storage devices through the communication link based on a CAN or an IEC61850. The operation analysis results using the developed hardware simulator confirm the ability of the DC micro-grid to supply the electric power to end users.

• 전기학회논문지
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• 제63권4호
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• pp.559-564
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• 2014

A microgrid as a small scale power system is operated by the grid-connected mode and islanded mode. It is anticipated that the battery energy storage system (BESS) is able to be applied to the microgrid for stable power control, such as tie-line and smoothing control in the grid-connected mode and voltage and frequency control in the islanded mode. In this paper, a digital signal processor (DSP), Two BESS controllers based on TMS320F28335 of a microgrid are implemented and are tested to show control performance in the hardware-in-the loop simulation (HILS) system.

• Journal of Computing Science and Engineering
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• 제11권2호
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• pp.69-77
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• 2017

Recent GPUs have adopted cache memory to benefit general-purpose GPU (GPGPU) programs. However, unlike CPU programs, GPGPU programs typically have considerably less temporal/spatial locality. Moreover, the L1 data cache is used by many threads that access a data size typically considerably larger than the L1 cache, making it critical to bypass L1 data cache intelligently to enhance GPU cache performance. In this paper, we examine GPU cache access behavior and propose a simple hardware-based GPU cache bypassing method that can be applied to GPU applications without recompiling programs. Moreover, we introduce a hybrid method that integrates static profiling information and hardware-based bypassing to further enhance performance. Our experimental results reveal that hardware-based cache bypassing can boost performance for most benchmarks, and the hybrid method can achieve performance comparable to state-of-the-art compiler-based bypassing with considerably less profiling cost.