• ETRI Journal
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• 제33권4호
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• pp.611-620
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• 2011

Since card-type one-time password (OTP) generators became available, power and area consumption has been one of the main issues of hardware OTPs. Because relatively smaller batteries and smaller chip areas are available for this type of OTP compared to existing token-type OTPs, it is necessary to implement power-efficient and compact dedicated OTP hardware modules. In this paper, we design and implement a low-power small-area hardware OTP generator based on the Advanced Encryption Standard (AES). First, we implement a prototype AES hardware module using a 350 nm process to verify the effectiveness of our optimization techniques for the SubBytes transform and data storage. Next, we apply the optimized AES to a real-world OTP hardware module which is implemented using a 180 nm process. Our experimental results show the power consumption of our OTP module using the new AES implementation is only 49.4% and 15.0% of those of an HOTP and software-based OTP, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권2호
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• pp.127-138
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• 2012

In this paper, we propose a real-time virtual re-convergence hardware platform especially to reduce the visual fatigue caused by stereoscopy. Our unique idea to reduce visual fatigue is to utilize the virtual re-convergence based on the optimized disparity-map that contains more depth information in the negative disparity area than in the positive area. Our virtual re-convergence hardware platform, which consists of image rectification, disparity estimation, depth post-processing, and virtual view control, is realized in real time with 60 fps on a single Xilinx Virtex-5 FPGA chip.

• 대한의용생체공학회:의공학회지
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• 제27권5호
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• pp.282-290
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• 2006

We have developed a multi band digital hearing aid algorithm emphasizing feedback cancellation and a hardware module to evaluate the performance of our algorithm. The hearing aids should be able to compensate for individual hearing loss characteristics of hearing impaired person. Thus hearing aids need the function of multi-bands amplification and the capabilities of feedback cancellation that can remove howling caused by acoustic feedback. In this paper, we proposed a digital hearing aid algorithm which has multi-bands compensation using modified discrete cosine transform (MDCT) and can efficiently remove acoustic feedbacks. Moreover, we have developed digital hearing aid hardware module, which can evaluate hearing aid algorithms in real time operation. The developed algorithm and hardware module were verified through computer simulation and clinical tests. Through operational experiments, good performances in real time operation environment and an efficient howling cancellation were also observed. The developed hardware module can operate in stable condition and it is expected to become a good hardware platform for developing hearing aid algorithms.

• Journal of information and communication convergence engineering
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• 제18권1호
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• pp.1-7
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• 2020

This paper proposes a fast-processing and low-cost hardware multiple input multiple output (MIMO) channel emulator. The channel emulator is an important component of hardware-based simulation systems. The novelty of this work is the use of sharing and pipelining functions to reduce hardware resource utilization while maintaining a high sample rate. In our proposed emulator, the samples are created sequentially and interpolated to ensure the sample rate is equal to the base band rate. The proposed 4 × 4 MIMO requires low-cost hardware resource so that it can be implemented on a single field-programmable gate array (FPGA) chip. An implementation on Xilinx Virtex-7 VX980T was found to occupy 10.47% of the available configurable slice registers and 12.58% of the FPGA's slice lookup tables. The maximum frequency of the proposed emulator is 758.064 MHz, so up to 560 different paths can be processed simultaneously to generate 560 × 758 million × 2 × 32 bit complex-valued fading samples per second.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.1797-1801
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• 2004

In this paper we show the hardware testbed and software simulator of multi function array radar (MFAR). The hardware MFAR is simple and flexible hardware to implement various radar beamforming and detecting algorithms. To overcome the limitation of hardware MFAR, the software simulator is proposed. User can simulate radar under the various environment conditions adjusting the parameter of simulator. User can set environment of radar, such as the location and velocity of target, jammer and the terrain clutter. The radar use various probing pulses and supports two operation mode, surveillance and tracking mode.

• 한국정보통신학회논문지
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• 제24권8호
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• pp.1109-1112
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• 2020

This paper presents a low cost hardware message passing engine of enhanced atomic pipelined broadcast based on processing node status. In this algorithm, the previous atomic pipelined broadcast algorithm is modified to reduce the waiting time until next broadcast communication. For this, the processor change the transmission order of processing nodes based on the nodes' communication channel. Also, the hardware message passing engine architecture of the proposed algorithm is modified to be adopted to multi-core processor. The synthesized logic area of the proposed hardware message passing engine was reduced by about 16%, compared by the pre-existing hardware message passing engine.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2009년도 추계학술발표대회
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• pp.67-68
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• 2009

Increasing use of embedded systems has made many improvements on hardware development for specific purpose. Hardware changes are more expensive and harder to implement rather than software changes. Developers need tools to do design and testing of new hardware. Many simulation tools have been made to mimic the hardware and allow developer to test programs on top of new hardware. Virtual Development Environment for Embedded Software (VDEES) is one of the alternatives available. It provides an open source based platform and an Integrated Development Environment (IDE) that can be used to build and testing newly made component, faster and at low-cost.

• 한국정보기술학회 영문논문지
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• 제8권2호
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• pp.13-25
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• 2018

The paper analyzes the sum spectral efficiency (SE) for a heterogeneous cellular network (HetNet) which has the backhaul, provided with wireless full-duplex massive multiple-input multiple-out (MIMO) with hardware distortions. We derive approximate expressions to obtain the uplink/downlink sum SE of the backhaul. The analytic results have been shown to be exact when compared to Monte Carlo simulations. From the analysis, it is shown that the desired signal and the hardware distortion noise have the same order. The sum SE generally improves when the number of receive antennas increases but degrades when the hardware quality reduces. A sum SE performance ceiling is introduced by the hardware quality level.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제13권5호
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• pp.2357-2380
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• 2019

In this paper, we investigate the impact of hardware impairments (HWIs) on the performance of a downlink massive MIMO system. We consider a single-cell system with maximum ratio transmission (MRT) as precoding scheme, and with all the HWIs characteristics such as phase noise, distortion noise, and amplified thermal noise. Based on the system model, we derive closed-form expressions for a typical user data rate under two scenarios: when a common local oscillator (CLO) is used at the base station and when separated oscillators (SLOs) are used. We also derive closed-form expressions for the downlink transmit power required for some desired per-user data rate under each scenario. Compared to the conventional system with ideal transceiver hardware, our results show that impairments of hardware make a finite upper limit on the user's downlink channel capacity; and as the number of base station antennas grows large, it is only the hardware impairments at the users that mainly limit the capacity. Our results also show that SLOs configuration provides higher data rate than CLO at the price of higher power consumption. An approach to minimize the effect of the hardware impairments on the system performance is also proposed in the paper. In our approach, we show that by reducing the cell size, the effect of accumulated phase noise during channel estimation time is minimized and hence the user capacity is increased, and the downlink transmit power is decreased.

• 전기전자학회논문지
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• 제25권1호
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• pp.10-14
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• 2021

본 논문에서는 기존 CIE1931 색 좌표계를 이용한 색상 보정 연산의 복잡성을 개선한 하드웨어를 제안한다. 기존 알고리즘은 연산 과정에서 큰 비트 수를 계산하기 위해 사용되는 4-Split Multiply 연산으로 인해 하드웨어가 커지는 단점이 있다. 제안하는 알고리즘은 기존 알고리즘의 정의된 R2X, X2R 연산을 미리 계산하여 하나의 행렬로 만들어 영상에 적용함으로써 연산량 감소와 하드웨어 크기 감소가 가능하다. Verilog로 설계된 하드웨어의 Xilinx 합성 결과를 비교함으로써 하드웨어 자원 감소와 4K 환경 실시간 처리를 위한 성능을 확인할 수 있다. 또한, FPGA 보드에서의 실행 결과를 제시함으로써 하드웨어 탑재 동작을 검증하였다.