• Title/Summary/Keyword: Hardware Cost Estimation

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A VLSI architecture for fast motion estimation algorithm (고속 움직임 추정 알고리즘에 적합한 VLSI 구조 연구)

  • 이재헌;라종범
    • Proceedings of the IEEK Conference
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    • 1998.06a
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    • pp.717-720
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    • 1998
  • In this paper, we propose a VLSI architecture for implementing a crecently proposed fast block matching algorithm, which is called the HSBMA3S. The proposed architecture consists of a systolic array based basic unit and two shift register arrays. And it covers a search range of -32 ~+31. By using a basic unit repeatedly, we can redcue the number of gates. To implement the basic unit, we can select one among various conventional systolic arrays by trading-off between speed and hardware cost. In this paper, the architecture for the basic unit is selected so that the hardware cost can be minimized. The proposed architecture is fast enough for low bit-rate applications (frame size of 352x288, 30 frames/sec) and can be implemented by less than 20,000 gates. Moreover, by simply modifying the basic unit, the architecture can be used for the higher bit-rate application of the frame size of 720*480 and 30 frames/sec.

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A Study on the Factors of the Hardware Cost Estimation for Service Robot Development (서비스 로봇 개발의 하드웨어 비용추정을 위한 항목 도출에 관한 연구)

  • Lee, Jungsoo;Sohn, Dongseop;Choi, Yeon-Seo;Park, Myeongjun;Min, Jeongtack
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.19 no.5
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    • pp.35-44
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    • 2018
  • The purpose of this study was to derive the factors that affect the development cost and the priority/weight of effectiveness in the pre-development stage of a service robot to estimate the development cost. In particular, the functions of service robots vary according to the field of application, and their prices are not only different but most of them are small-scale production; hence, a cost estimation is necessary. In this research, the factors affecting the service robot development cost in the process of service robot development and adding functions are classified as a functional factor while the factors that affect the entire development cost due to environmental causes, in which the service robot is operated or in the development process, are classified as an adjustment factor. The FGI was conducted to derive the factors and a Delphi survey was conducted among 84 domestic experts to determine the weights of the factors. As a result of the analysis, six functional factors (41 detailed criteria) and five adjustment factors (17 criteria) were derived, the cost weight and rank of the factors were suggested. This study suggests that the development cost of the service robot can be used as a decision-making strategy to select the operation functions in the development process, and can be utilized as an essential tool for the service robot development.

FFT-Based Position Estimation in Switched Reluctance Motor Drives

  • Ha, Keunsoo;Kim, Jaehyuck;Choi, Jang Young
    • Journal of Magnetics
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    • v.19 no.1
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    • pp.90-100
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    • 2014
  • Position estimation that uses only active phase voltage and current is presented, to perform high accuracy position sensorless control of a SRM drive. By extracting the amplitude of the first switching harmonic terms of phase voltage and current for a PWM period through Fast Fourier Transform (FFT), the flux-linkage and position are estimated without external hardware circuitry, such as a modulator and demodulator, which result in increased cost, as well as large position estimation error, produced when the motional back EMF is ignored near zero speed. A two-phase SRM drive system, consisting of an asymmetrical converter and a conventional closed-loop PI current controller, is utilized to validate the performance of the proposed position estimation scheme in comprehensive operating conditions. It is shown that the estimated values very closely track the actual values, in dynamic simulations and experiments.

A hardware architecture based on the NCC algorithm for fast disparity estimation in 3D shape measurement systems (고밀도 3D 형상 계측 시스템에서의 고속 시차 추정을 위한 NCC 알고리즘 기반 하드웨어 구조)

  • Bae, Kyeong-Ryeol;Kwon, Soon;Lee, Yong-Hwan;Lee, Jong-Hun;Moon, Byung-In
    • Journal of Sensor Science and Technology
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    • v.19 no.2
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    • pp.99-111
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    • 2010
  • This paper proposes an efficient hardware architecture to estimate disparities between 2D images for generating 3D depth images in a stereo vision system. Stereo matching methods are classified into global and local methods. The local matching method uses the cost functions based on pixel windows such as SAD(sum of absolute difference), SSD(sum of squared difference) and NCC(normalized cross correlation). The NCC-based cost function is less susceptible to differences in noise and lighting condition between left and right images than the subtraction-based functions such as SAD and SSD, and for this reason, the NCC is preferred to the other functions. However, software-based implementations are not adequate for the NCC-based real-time stereo matching, due to its numerous complex operations. Therefore, we propose a fast pipelined hardware architecture suitable for real-time operations of the NCC function. By adopting a block-based box-filtering scheme to perform NCC operations in parallel, the proposed architecture improves processing speed compared with the previous researches. In this architecture, it takes almost the same number of cycles to process all the pixels, irrespective of the window size. Also, the simulation results show that its disparity estimation has low error rate.

Hardware Implementation of Past Multi-resolution Motion Estimator for MPEG-4 AVC (MPEG-4 AVC를 위한 고속 다해상도 움직임 추정기의 하드웨어 구현)

  • Lim Young-hun;Jeong Yong-jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.11C
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    • pp.1541-1550
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    • 2004
  • In this paper, we propose an advanced hardware architecture for fast multi-resolution motion estimation of the video coding standard MPEG-1,2 and MPEG-4 AVC. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and fast operation by using the shared memory, the special ram architecture, the motion vector for 4 pixel x 4 pixel, the spiral search and so on. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur Altera FPGA and also by ASIC synthesis using Samsung 0.18 m CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 140 MHz, processing more than 1,100 QCIF video frames or 70 4CIF video frames per second. The hardware is going to be used as a core module when implementing a complete MPEG-4 AVC video encoder ASIC for real-time multimedia application.

Mobile Device NDF(No Defect Found) Cost Estimation (모바일 디바이스의 원인불명고장에 관한 비용 추정)

  • Lee, Jewang;Lee, Jungwoo;Han, Chang Hee
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.44 no.2
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    • pp.102-114
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    • 2021
  • NDF (No Defect Found) is a phenomenon in which defects have been found in the manufacturing, operation and use of a product or facility, but phenomenon of defects is not reproduced in the subsequent investigation system or the cause of the defects cannot be identified. Recently, with the development of the fourth industrial revolution, convergence of hardware and software technologies in various fields is spreading to products such as aircraft, home appliances, and mobile devices, and the number of parts is increasing due to functional convergence. The application of such convergence technologies and the increase in the number of parts are major factors that lead to an increase in NDF phenomena. NDF phenomena have a significant negative impact on cost, reliability, and reliability for both manufacturers, service providers and operators. On the other hand, due to the nature of NDF phenomena such as difficult and intermittent cause identification and ambiguity in judgment, it is common to underestimate the cost of NDF or fail to take appropriate countermeasures in corporate management. Therefore, in this paper, we propose a methodology for estimating NDF costs by the PAF model which is a quality cost analysis model and ABC (Activity Based Costing) technique. The methodology of this study suggests a detailed procedure and the concept to accurately estimate the NDF costs, using ABC analysis, accounting system information, and IT system data. In addition case studies have validated the methodology. We think this could be a valid methodology to refer to when estimating the cost of other parts. And, it is meaningful to provide important judgment information in the decision-making process based on quality management and ultimately reduce NDF costs by visualizing them separately by major variable factors.

A study on the design of conductor stringing for KEPCO 765kV Transmission Lines (한전 765 kV 송전선로 전선가선설계에 관한 검토)

  • Park, K.H.;Kim, Y.W.;Won, B.J.
    • Proceedings of the KIEE Conference
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    • 1995.07c
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    • pp.1330-1331
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    • 1995
  • This paper deals with the design of conductor stringing of KEPCO 765kV transmission line. The main subject in the design of conductor stringing is the determination on what the stringing tension is. According to the stringing tension, the weight and height of towers and the strength necessary for conductor, hardware, insulator vary, and the construction cost and the reliability of tower are affected largely. Therefore, in order to determine the optimum condition for stringing conductors, We appraised various items : estimation of economic comparision, strength appraisal of conductor, hardware, insulator, etc. After studying these entirely, we present the condition of condutor stringing for KEPCO 765kV transmission line.

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Purposes, Results, and Types of Software Post Life Cycle Changes

  • Koh, Seokha;Han, Man Pil
    • Journal of Information Technology Applications and Management
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    • v.22 no.3
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    • pp.143-167
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    • 2015
  • This paper addresses the issue how the total life cycle cost may be minimized and how the cost should be allocated to the acquirer and developer. This paper differentiates post life cycle change (PLCC) endeavors from PLCC activities, rigorously classifies PLCC endeavors according to the result of PLCC endeavors, and rigorously defines the life cycle cost of a software product. This paper reviews classical definitions of software 'maintenance' types and proposes a new typology of PLCC activities too. The proposed classification schemes are exhaustive and mutually exclusive, and provide a new paradigm to review existing literatures regarding software cost estimation, software 'maintenance,' software evolution, and software architecture from a new perspective. This paper argues that the long-term interest of the acquirer is not protected properly because warranty period is typically too short and because the main concern of warranty service is given to removing the defects detected easily. Based on the observation that defects are caused solely by errors the developer has committed for software while defects are often induced by using for hardware (so, this paper cautiously proposes not to use the term 'maintenance' at all for software), this paper argues that the cost to remove defects should not be borne by the acquirer for software.

VLSI Design for Motion Estimation Based on Bit-plane Matching (비트 플레인 정합에 의한 움직임 추정기의 VLSI 설계)

  • Go, Yeong-Gi;O, Hyeong-Cheol;Go, Seong-Je
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.38 no.5
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    • pp.509-517
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    • 2001
  • Full-search algorithm requires large amount of computation which causes time delay or very complex hardware architecture for real time implementation. In this paper, we propose a fast motion estimator based on bit-plane matching, which reduce the computational complexity and the hardware cost. In the proposed motion estimator, the conventional motion estimation algorithms are applied to the binary images directly extracted from the video sequence. Furthermore, in the proposed VLSI motion estimator, we employ a Pair of processing cores that calculate the motion vector continuously By controlling the data flow in a systolic fashion using the internal shift registers in the processing cores, we avoid using SRAM (local memory) so that we remove the time overhead for accessing the local memory and adopt lower-cost fabrication technology. We modeled and tested the proposed motion estimator in VHDL, and then synthesized the whole system which has been integrated in a 0.6-$\mu$m triple-metal CMOS chip of size 8.15 X 10.84$\textrm{mm}^2$.

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A VLSI Architecture for Fast Motion Estimation Algorithm (고속 움직임 추정 알고리즘에 적합한 VLSI 구조 연구)

  • 이재헌;나종범
    • Journal of Broadcast Engineering
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    • v.3 no.1
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    • pp.85-92
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    • 1998
  • The block matching algorithm is the most popular motion estimation method in image sequence coding. In this paper, we propose a VLSI architecture. for implementing a recently proposed fast bolck matching algorith, which uses spatial correlation of motion vectors and hierarchical searching scheme. The proposed architecture consists of a basic searching unit based on a systolic array and two shift register arrays. And it covers a search range of -32~ +31. By using the basic searching unit repeatedly, it reduces the number of gatyes for implementation. For basic searching unit implementation, a proper systolic array can be selected among various conventional ones by trading-off between speed and hardware cost. In this paper, a structure is selected as the basic searching unit so that the hardware cost can be minimized. The proposed overall architecture is fast enough for low bit-rate applications (frame size of $352{\times}288$, 3Oframes/sec) and can be implemented by less than 20,000 gates. Moreover, by simply modifying the basic searching unit, the architecture can be used for the higher bit-rate application of the frame size of $720{\times}480$ and 30 frames/sec.

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