• KSII Transactions on Internet and Information Systems (TIIS)
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• 제14권12호
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• pp.4648-4663
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• 2020

This paper proposes the Lempel-Ziv 4(LZ4) compression accelerator optimized for scale-out servers in data centers. In order to reduce CPU loads caused by compression, we propose an accelerator solution and implement the accelerator on an Field Programmable Gate Array(FPGA) as heterogeneous computing. The LZ4 compression hardware accelerator is a fully pipelined architecture and applies 16 dictionaries to enhance the parallelism for high throughput compressor. Our hardware accelerator is based on the 20-stage pipeline and dictionary architecture, highly customized to LZ4 compression algorithm and parallel hardware implementation. Proposing dictionary architecture allows achieving high throughput by comparing input sequences in multiple dictionaries simultaneously compared to a single dictionary. The experimental results provide the high throughput with intensively optimized in the FPGA. Additionally, we compare our implementation to CPU implementation results of LZ4 to provide insights on FPGA-based data centers. The proposed accelerator achieves the compression throughput of 639MB/s with fine parallelism to be deployed into scale-out servers. This approach enables the low power Intel Atom processor to realize the Hadoop storage along with the compression accelerator.

• 전기전자학회논문지
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• 제24권1호
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• pp.186-193
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• 2020

본 논문에서는 Zynq SoC 환경에서 재구성 가능한 하드웨어 가속기를 지원하는 멀티쓰레딩 시스템을 제안한다. 압축된 정지 영상의 픽셀 데이터를 복원하는 고성능 JPEG 디코더를 구현하고 2D-IDCT 함수를 재구성 가능한 하드웨어 가속기로 설계하여 성능을 검증한다. 구현된 시스템에서 최대 4개의 재구성 가능한 하드웨어 가속기는 소프트웨어 쓰레드와 동기화되어 연산을 수행할 수 있으며 이미지 해상도와 압축률에 따라 다른 성능 향상을 보인다. 1080p 해상도 영상의 경우 17:1의 압축률에서 최대 79.11배의 성능 향상과 99fps의 throughput 속도를 보여준다.

• IEIE Transactions on Smart Processing and Computing
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• 제5권5호
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• pp.310-318
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• 2016

Emerging technologies such as the Internet of Things (IoT) and the Advanced Driver Assistant System (ADAS) often have image transmission functions with tough constraints, like low power and/or low delay, which require that they adopt line-based, low memory compression methods instead of existing frame-based image compression standards. Bit rate control in the conventional frame-based compression systems requires a lot of hardware resources when the scope of handled data falls at the frame level. On the other hand, attempts to reduce the heavy hardware resource requirement by focusing on line-level processing yield uneven image quality through the frame. In this paper, we propose a bit rate control that maintains consistency in image quality through the frame and improves the legibility of text regions. To find the line characteristics, the proposed bit rate control tests each line for ease of compression and the existence of text. Experiments on the proposed bit rate control show peak signal-to-noise ratios (PSNRs) similar to those of conventional bit rate controls, but with the use of significantly fewer hardware resources.

• ETRI Journal
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• 제29권4호
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• pp.530-532
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• 2007

This paper presents a simple method to implement a complete on-line portable wireless holter including an electrocardiogram (ECG) monitoring, processing, and communication protocol. The proposed algorithm significantly reduces the hardware resources of threshold estimation for ECG compression, using the standard deviation updated with each new input signal sample. The new method achieves superior performance in terms of hardware complexity, channel occupation and memory requirements, while keeping the ECG quality at a clinically acceptable level.

• International journal of advanced smart convergence
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• 제6권1호
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• pp.68-75
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• 2017

In this paper, a particular application of digital photos, remote sensing, remote shooting air moving, high-resolution and high compression of medical images required by remote shooting of JPEG2000 standard applied in the field of hardware design, production was implemented. JPEG2000 standard for image compression using the software implementation of the processing speed is very slow compared to conventional JPEG disadvantages, and also the standard of JPEG2000 DWT (Discrete wavelet transform) to improve the level of compression for image data if processing speed is a phenomenon that has degraded. In order to solve these JPEG2000 compression / decompression groups were designed and applied. In this paper, the optimal JPEG2000 compression / reservoir hardware by changing the level for still image compression, faster computation speed and quality has shown improvement.

• 한국정보과학회논문지:시스템및이론
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• 제30권10호
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• pp.586-594
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• 2003

X-Match 알고리즘은 비교적 간단하여 하드웨어로 구현하는 데에 적합한 무손실 압축 알고리즘이다. X-Match 알고리즘은 사이클 당 32비트의 압축이 가능하므로 고속 압축에 적합하다. 그렇지만 버스 폭이 증가됨에 따라서 이에 맞추어서 압축 단위를 증가시킬 필요가 있게 되었다. 본 논문에서는 X-Match 알고리즘을 병렬로 수행하여 압축 속도를 2배 향상시키고 X-Match 알고리즘 거의 비슷한 압축률을 제공하는 협동 병렬 X-Match 알고리즘, 즉 X-MatchCP 알고리즘을 제안한다. 기존의 병렬 X-Match 알고리즘이 X-Match 알고리즘을 병렬로 수행할 매에 각자의 사전을 검색하는 데 비해서 X-MatchCP 알고리즘에서는 X-Match 알고리즘이 병렬로 수행되지만 전체 사전을 검색하여 매칭빈도를 높이도록 하였고 run-length 부호화도 두 워드에 대해서 한꺼번에 하는 방식으로 서로 협동하면서 동작한다 메모리 데이타와 파일 자료를 사용한 시뮬레이션 결과 X-MatchCP 알고리즘은 같은 사전 크기의 X-Match 알고리즘과 거의 비슷한 압축률을 보였다. 그리고 X-MatchCP 알고리즘의 하드웨어 구현을 위한 전체적인 구조 설계를 Verilog 언어를 사용하여 수행하였다.

• 한국통신학회논문지
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• 제41권11호
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• pp.1502-1506
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• 2016

HEVC (High Efficiency Video Coding)는 최근에 제안된 비디오 압축 표준으로서 이전의 비디오 압축 표준보다 두 배 이상의 부호화 효율을 가진다. 다양한 종류의 인트라 예측 블록과 모드는 HEVC의 높은 압축 성능과 연산 복잡도 증가의 주요 요인이다. 본 논문은 파이프라인과 인터리빙 기술을 사용하여 하드웨어 자원의 요구조건을 줄이는 반면 효율과 성능은 향상시킨 HEVC 용 인트라 예측 하드웨어 구조를 제시한다.

• 전자공학회논문지C
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• 제34C권3호
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• pp.23-36
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• 1997

In tis paper, sthe new data model for the hardware implementation of lempel-ziv compression algorithm was proposed. Traditional model generates the codeword which consists of 3 bytes, the last symbol, the position and the matched length. MSB (most significant bit) of the last symbol is the comparession flag and the remaining seven bits represent the character. We confined the value of the matched length to 128 instead of 256, which can be coded with seven bits only. In the proposed model, the codeword consists of 2 bytes, the merged symbol and the position. MSB of the merged symbol is the comression flag. The remaining seven bits represent the character or the matched length according to the value of the compression flag. The proposed model reduces the compression ratio by 5% compared with the traditional model. The proposed model can be adopted to the existing hardware architectures. The incremental factors of the compression ratio are also analyzed in this paper.

• ETRI Journal
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• 제33권1호
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• pp.140-143
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• 2011

Recent test data compression techniques raise concerns regarding power dissipation and compression efficiency. This letter proposes a new test data compression scheme, twin symbol encoding, that supports block division skills that can reduce hardware overhead. Our experimental results show that the proposed technique achieves both a high compression ratio and low-power dissipation. Therefore, the proposed scheme is an attractive solution for efficient test data compression.

• 디지털산업정보학회논문지
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• 제17권4호
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• pp.53-62
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• 2021

Deep learning models such as convolutional neural networks and recurrent neual networks process a huge amounts of data, so they require a lot of storage and consume a lot of time and power due to memory access. Recently, research is being conducted to reduce memory usage and access by compressing data using the feature that many of deep learning data are highly sparse and localized. In this paper, we propose a compression-decompression method of storing only the non-zero data and the location information of the non-zero data excluding zero data. In order to make the location information of non-zero data, the matrix data is divided into sections uniformly. And whether there is non-zero data in the corresponding section is indicated. In this case, section division is not executed only once, but repeatedly executed, and location information is stored in each step. Therefore, it can be properly compressed according to the ratio and distribution of zero data. In addition, we propose a hardware structure that enables compression and decompression without complex operations. It was designed and verified with Verilog, and it was confirmed that it can be used in hardware deep learning accelerators.