• Proceedings of the Korean Institute of Resources Recycling Conference
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• 2003.10a
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• pp.185-189
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• 2003

The effect of surface roughness of the substrate on HF-CVD diamond coating was researched. The surface roughness was changed variously by electro-chemical etching conditions. The etching process acted to remove the metallic cobalt from the WC-Co. Diamond nucleation density was higher in etched the substrate. Therefore, the etching process was effective in both Co-removal and higher surface roughness, leading to the improving the diamond nucleation and deposition.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.8
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• pp.700-704
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• 2003

This paper describes on characteristics of 2" 3C-SiC wafer bonding using PECVD (plasma enhanced chemical vapor deposition) oxide and HF (hydrofluoride acid) for SiCOI (SiC-on-Insulator) structures and MEMS (micro-electro-mechanical system) applications. In this work, insulator layers were formed on a heteroepitaxial 3C-SiC film grown on a Si (001) wafer by thermal wet oxidation and PECVD process, successively. The pre-bonding of two polished PECVD oxide layers made the surface activation in HF and bonded under applied pressure. The bonding characteristics were evaluated by the effect of HF concentration used in the surface treatment on the roughness of the oxide and pre-bonding strength. Hydrophilic character of the oxidized 3C-SiC film surface was investigated by ATR-FTIR (attenuated total reflection Fourier transformed infrared spectroscopy). The root-mean-square suface roughness of the oxidized SiC layers was measured by AFM (atomic force microscope). The strength of the bond was measured by tensile strength meter. The bonded interface was also analyzed by IR camera and SEM (scanning electron microscope), and there are no bubbles or cavities in the bonding interface. The bonding strength initially increases with increasing HF concentration and reaches the maximum value at 2.0 ％ and then decreases. These results indicate that the 3C-SiC wafer direct bonding technique will offers significant advantages in the harsh MEMS applications.ions.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.164-167
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• 2002

SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS applications because of its application possibility in harsh environments. This paper presents on pre-bonding according to HF pre-treatment conditions in SiC wafer direct bonding using PECVD oxide. The characteristics of bonded sample were measured under different bonding conditions of HF concentration, and applied pressure. The 3C-SiC epitaxial films grown on Si(100) were characterized by AFM and XPS, respectively. The bonding strength was evaluated by tensile strength method. Components existed in the interlayer were analyzed by using FT-IR. The bond strength depends on the HF pre-treatment condition before pre-bonding (Min : 5.3 kgf/$\textrm{cm}^2$∼Max : 15.5 kgf/$\textrm{cm}^2$).

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.2020-2022
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• 2002

SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS fileds because of its application possibility in harsh environements. This paper presents on pre-bonding according to HF pre-treatment conditions in SiC wafer direct bonding using PECVD oxide. The PECVD oxide was characterized by XPS and AFM, respectively. The characteristics of bonded sample were measured under different bonding conditions of HF concentration and applied pressure, respectively. The bonding strength was evaluated by tensile strength method. Components existed in the interlayer were analyzed by using FT-IR. The bond strength depends on the HF pre-treatment condition before pre-bonding (Min : 5.3 kgf/$cm^2{\sim}$ Max : 15.5 kgf/$cm^2$).

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.45-51
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• 2004

We have proposed a new shallow trench isolation (STI) process using flowable oxide (F-oxide) chemical vapor deposition (CVD) for DRAM application and it was successfully developed. The combination of F-oxide CVD and HDP CVD is thought to be the superior STI gap-filling process for next generation DRAM fabrication because F-oxide not only improves STI gap-filling capability, but also the reduced local stress by F-oxide in narrow trenches leads to decrease in junction leakage and gate induced drain leakage (GIDL) current. Finally, this process increased data retention time of DRAM compared to HDP STI. However, a serious failure occurred by symphonizing its structural dependency of deposited thickness with poor resistance against HF chemicals. It could be suppressed by reducing the flow time during F-oxide deposition. It was investigated collectively in terms of device yield. In conclusion, the combination of F-oxide and HDP oxide is the very promising technology for STI gap filling process of sub-100nm DRAM technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.387-390
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• 2002

SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS(micro electro mechanical system) fields because of its application possibility in harsh environments. This paper presents pre-bonding techniques with variation of HF pre-treatment conditions for 2 inch SiC wafer direct bonding using PECVD(plasma enhanced chemical vapor deposition) oxide. The PECVD oxide was characterized by XPS(X-ray photoelectron spectrometer) and AFM(atomic force microscopy). The characteristics of the bonded sample were measured under different bonding conditions of HF concentration and an applied pressure. The bonding strength was evaluated by the tensile strength method. The bonded interface was analyzed by using IR camera and SEM(scanning electron microscope). Components existed in the interlayer were analyzed by using FT-IR(fourier transform infrared spectroscopy). The bonding strength was varied with HF pre-treatment conditions before the pre-bonding in the range of $5.3 kgf/cm^2$ to $15.5 kgf/cm^2$

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.151-152
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• 2007

탄소나노튜브(CNTs)는 우수한 물리적, 화학적, 기계적 특성으로 다양한 분야에서 연구가 진행 되고있다. 특히, field emission displays (FEDs)로의 응용을 위해서는 기본적으로 sodalime glass 위에 직접 CNTs를 성장시켜야 하며, 소자 응용을 위해 기판인 sodalime glass를 왜곡시키는 온도보다 낮은 온도에서 CNT의 수직 성장이 이루어져야 한다. 본 연구에서는 Hot-filament plasma enhanced chemical vapor deposition (HF-PECVD)를 이용하여 합성온도를 400, 450, 500, $550^{\circ}C$로 변화시켰으며 촉매 층인 Ni의 두께를 5~40 nm까지 조절하여 탄소나노튜브를 합성하였다. 저온에서 합성된 탄소나노튜브는 FE-SEM을 이용하여 성장 형태 및 표면 특성을 확인하였으며, 미세구조는 HR-TEM을 이용하여 확인하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.263-263
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• 2016

최근 반도체 시장에서는 저비용으로 고성능 박막 트랜지스터(TFT)를 제작하기 위한 다양한 기술들이 연구되고 있다. 먼저, 재료적인 측면에서는 비정질 상태에서도 높은 이동도와 가시광선 영역에서 투명한 특성을 가지는 산화물 반도체가 기존의 비정질 실리콘이나 저온 폴리실리콘을 대체하여 차세대 디스플레이의 구동소자용 재료로 많은 주목받고 있다. 또한, 공정적인 측면에서는 기존의 진공장비를 이용하는 PVD나 CVD가 아닌 대기압 상태에서 이루어지는 용액 공정이 저비용 및 대면적화에 유리하고 프리커서의 제조와 박막의 증착이 간단하다는 장점을 가지기 때문에 활발한 연구가 이루어지고 있다. 특히 산화물 반도체 중에서도 indium-gallium-zinc oxide (IGZO)는 비교적 뛰어난 이동도와 안정성을 나타내기 때문에 많은 연구가 진행되고 있지만, 산화물 반도체 기반의 박막 트랜지스터가 가지는 문제점 중의 하나인 문턱전압의 불안정성으로 인하여 상용화에 어려움을 겪고 있다. 따라서, 본 연구에서는 기존의 산화물 반도체의 불안정한 문턱전압의 문제점을 해결하기 위해 마이크로웨이브 열처리를 적용하였다. 또한, 기존의 IGZO에서 suppressor 역할을 하는 값비싼 갈륨(Ga) 대신, 저렴한 지르코늄(Zr)과 하프늄(Hf)을 각각 적용시켜 용액 공정 기반의 Zr-In-Zn-O (ZIZO) 및 Hf-In-Zn-O (HIZO) TFT를 제작하여 시간에 따른 문턱 전압의 변화를 비교 및 분석하였다. TFT 소자는 p-Si 위에 습식산화를 통하여 100 nm 두께의 $SiO_2$가 열적으로 성장된 기판 위에 제작되었다. 표준 RCA 세정을 진행하여 표면의 오염 및 자연 산화막을 제거한 후, Ga, Zr, Hf 각각 suppressor로 사용한 IGZO, ZIZO, HIZO 프리커서를 이용하여 박막을 형성시켰다. 그 후 소스/드레인 전극 형성을 위해 e-beam evaporator를 이용하여 Ti/Al을 5/120 nm의 두께로 증착하였다. 마지막으로, 후속 열처리로써 마이크로웨이브와 퍼니스 열처리를 진행하였다. 그 결과, 기존의 퍼니스 열처리와 비교하여 마이크로웨이브 열처리된 IGZO, ZIZO 및 HIZO 박막 트랜지스터는 모두 뛰어난 안정성을 나타냄을 확인하였다. 결론적으로, 본 연구에서 제안된 마이크로웨이브 열처리된 용액공정 기반의 ZIZO와 HIZO 박막 트랜지스터는 추후 디스플레이 산업에서 IGZO 박막 트랜지스터를 대체할 수 있는 저비용 고성능 트랜지스터로 적용될 것으로 기대된다.

• Journal of the Korean Ceramic Society
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• v.52 no.6
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• pp.429-434
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• 2015

This study investigates the macroscopic wear behaviors of C/C and C/C-SiC composites coated with hafnium carbide (HfC). To improve the wear resistance of C/C composites, low-pressure chemical vapor deposition (LPCVD) was used to obtain HfC coating. The CVD coatings were deposited at various deposition temperatures of 1300, 1400, and $1500^{\circ}C$. The effect of the substrate material (the C/C substrate, the C/C-CVR substrate, or the C/C-SiC substrate deposited by LSI) was also studied to improve the wear resistance. The experiment used the ball-on-disk method, with a tungsten carbide (WC) ball utilized as an indenter to evaluate the wear behavior. The HfC coatings were found to effectively improve the wear resistance of C/C and C/C-SiC composites, compared with the case of a non-coated C/C composite. The former showed lower friction coefficients and almost no wear loss during the wear test because of the presence of hard coatings. The wear scar width was relatively narrower for the C/C and C/C-SiC composites with hafnium coatings. Wear behavior was found to critically depend on the deposition temperature and the material. Thus, the HfC-coated C/C-SiC composites fabricated at deposition temperatures of $1500^{\circ}C$ showed the best wear resistance, a lower friction coefficient, and almost no loss during the wear test.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.171-171
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• 2003

공정기술의 향상으로 DRAM(dynamic random acess memory)의 고집적화가 이루어지고 있으며, 각 개별소자 및 셀 영역의 점유면적의 감소가 요구되어지고 있다. 따라서 기존에 사용하던 NO (Si$_3$N$_4$/SiO$_2$)박막보다 유전율이 높은 고유전물질에 대한 연구가 진행되고 있다. Ta$_2$O$_{5}$, $Y_2$O$_3$, HfO$_2$, ZrO$_2$,Nb$_2$O$_{5}$, BaTiO$_3$, SrTiO$_3$ 및 (BaSr)TiO등이 고유전물질로 연구되고 있는데 그 중 공정의 안정성, 누설전류의 우수성으로 인해 Ta$_2$O$_{5}$이 많이 연구되고 있다. 본 실험에서는 TiO$_2$가 8 mol%가 첨가된 Ta$_2$O$_{5}$의 열처리 온도에 따른 전기적, 유전특성을 살펴보려고 한다살펴보려고 한다