• Clean Technology
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• v.7 no.1
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• pp.13-25
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• 2001

With fast advancement of fine machineries and semiconductor industries in recent decades, the ultra-cleaning of organic chemicals, submicron particles from contaminated unit equipments and products such as silicon wafers becomes one of the most important steps for further advancement of such industries. To date, two kinds of ultra cleaning techniques are used; one is the wet-cleaning and the other is the dry cleaning. In case of wet cleaning, removal of organic contaminants and submicron particles is made by DIW with additives such as $H_2O_2$, $H_2SO_4$, HCl, $NH_4OH$ and HF, etc. While the wet cleaning method is most widely adopted for various occasions, it is inevitable to discharge significant amount of toxic waste waters in environment. Dry cleaning is an alternative method to mitigate environmental pollution of the wet cleaning with maintaining comparable degree of cleaning to the wet cleaning. Although there are various concept of dry cleaning have been devised, the dry cleaning with environmentally-benign solvent such as carbon dioxide proven to show high degree of cleaning from the contaminated porous surface as well as from the bare surface. Thus, special global attention has been placing on this technique since it has important advantages of simple process schemes and no environmentally concern, etc. Thus, this article critically reviews the state-of-the-art of the supercritical fluid drying with emphasis on the thermo-physical characteristics of the supercritical solvent, environmental gains compared to other dry cleaning methods, and the generic aspects of the basic design and processing engineering.

• Korean Journal of Materials Research
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• v.8 no.5
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• pp.464-469
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• 1998

HF 세정후 자연 산화막의 존재가 급속 열처리 장비를 이용, 아르곤 분위기에서 열처리할 때 티타늄 실리사이드 형성을 관찰하였다. 고분해능 단면 투과 전자 현미경 관찰 결과 기판 온도가 상온일 때 자연산화막(native oxide)이 존재함을 확인하였으며 기판 온도가 40$0^{\circ}C$일 때는 실리콘 기판과 티타늄 박막의 계면 부위에서 자연산화막, 티타늄 및 실리콘이 혼합된 비정질층이 존재함을 확인하였다. 티타늄을 증착하는 동안 기판 온도를 40$0^{\circ}C$로 유지했을 때는 C54~$TiSi_2$상이 형성되는데 요구되는 급속 열처리(Rapid Thermal Annealing : RTA)온도가 기판 온도를 상오느로 유지 했을 때보다 $100^{\circ}C$정도 감소함을 확인하였다. 이 같은 결과는 산소불순물을 함유한 비정질 층이 핵생성 자리를 제공하여 이 상의 형성이 촉진된다는 사실을 말한다. 기판온도 $400^{\circ}C$에서 형성된 티타늄 실리사이드막의 경우 비저항 $\mu$$\Omega$cm임을 확인하였다.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1069-1071
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• 1995

The electrical properties of Al/TiN/Ti contact are investigated at submicron contacts. The contact resistance and contact leakage current are dependent on metallization, surface dopant concentration, semiconductor surface treatment and contact plug ion implantation. In this paper, the contact resistance and contact leakage current are studied according to surface dopant concentration, semiconductor surface treatment and contact plug ion implantation at 0.8 micron contact. The contact resistance and contact leakage current increases with increasing substrate ion concentration. HF cleaning represents high contact resistance but low contact leakage current while CDE cleaning represents low contact resistance but high contact leakage current. Contact plug ion implantation decreases contact resistance but increases contact leakage current. Specially, RTA represents good electrical properties.

• Journal of the Semiconductor & Display Technology
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• v.3 no.2
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• pp.11-15
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• 2004

Scales, accumulated on some parts of semiconductor equipments such as sputters and CVD during the device fabrication processes, often lower the lifetime of the equipments and production yields. Thus, many equipment parts have be cleaned regularly. In this study, an attempt to establish an effective process to remove scales on the sidewall of collimators located inside the chamber of the sputter was made. The EDX analysis revealed that the scales were composed of Ti and TiN with the columnar structure. Through the trial-and-error experiments, it was found that the etching in the $HNO_3$:$H_2SO_4$:$H_2O$=4:2:4 solution for 5.5 hrs at $67^{\circ}C$, after the oxide removal in the HF solution, and the heat-treatment at $700^{\circ}C$ for 1 min., was the most effective process for the scale removal.

• Electrical & Electronic Materials
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• v.7 no.4
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• pp.294-299
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• 1994

CHF$_{3}$/CH$_{4}$Ar 플라즈마에 의해 형성된 산화막 식각 잔류물의 화학구조와 이 잔류물의 제거를 위한 세정방법을 x-ray photoelectron spectroscopy를 이용하여 조사하였다. 잔류무르이 구조는 CF$_{x}$-polymer와 Si-C, Si-O 결합으로 이루어진 SiO$_{y}$ C$_{z}$ 이었다. CF$_{4}$O$_{2}$ 플라즈마에 의한 silicon light etch는 산화막 식각 잔류물인 SiO$_{y}$ C$_{z}$ 층과 손상된 실리콘 표면을 제거하엿으며 NH$_{4}$OH-H$_{2}$O$_{2}$과 HF용액으로 완전히 제거되는 CF$_{x}$-polymer/SiO$_{x}$층을 남겼다. 100.angs.정도의 silicon light etch는 minority carrier life time과 thermal wave signal값을 초기 웨이퍼 수준까지 회복시켰으며 접합누설 전류도 거의 습식 식각 공정수준까지 감소시켰다.

• Clean Technology
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• v.8 no.3
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• pp.119-128
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• 2002

In the present study the membrane filtration characteristics of a commercially available synthetic water-based cutting oil through two kinds of ultrafiltration membranes (HF1-45-CM50 and HF1-43-CM100) with molecular weight cut-offs of 50,000 and 100,000, respectively, have been investigated in detail. Among these membranes, the hydrophilic one (HF1-45-CM50) was found to show a satisfactory result for both the permeate flux and the permeability of oil components, whereas the permeate flux obtained with the hydrophobic membrane (HF1-43-CM100) appears to be significantly low, indicating that synthetic cutting oil was easily wetted on the hydrophobic membrane surface and induced more membrane fouling. The effect of material characteristics of the membrane on the filtration characteristics was found to be much more significant compared with the mean pore size of the membrane. Backflushing by nitrogen gas was applied to reduce the formation of a gel layer and membrane fouling. With the hydrophilic membrane, the backflushing was found to increase the permeate flux, whereas the backflushing resulted in a decrease in flux for the hydrophobic membrane. The flux recovery was observed to be highest when the membranes fouled with waste synthetic cutting oil were immersed into a cleaning solution for more than 72 hours and then backflushed by nitrogen gas.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.4
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• pp.325-331
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• 2007

In this study, the inter-metal dielectric material of FSG was changed by low-k material in $0.13{\mu}m$ foundry-compatible technology (FCT) device process based on fluorinated silicate glass (FSG). Black diamond (BD) was used as a low-k material with a dielectric constant of 2.95 for optimization and yield-improvement of the low-k based device process. For yield-improvement in low-k based device process, some problems such as photoresist (PR) poisoning, damage of low-k in etch/ash/cleaning process, and chemical mechanical planarization (CMP) delamination must be solved. The PR poisoning was not observed in BD based device. The pressure in CMP process decreased to 2.8 psi to remove the CMP delamination for Cu-CMP and USG-CMP. $H_2O$ ashing process was selected instead of $O_2$ ashing process due to the lowest condition of low-k damage. NE14 cleaning after ashing process lot the removal of organic residues in vias and trenches was employed for wet process instead of dilute HF (DHF) process. The similar-state of SRAM yield was obtained in Cu/low-k process compared with the conventional $0.13{\mu}m$ FCT device by the optimization of these process conditions.

• Korean Chemical Engineering Research
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• v.51 no.6
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• pp.666-670
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• 2013

Recovery method of silicon wafer from defective products generated from manufacturing process of silicon solar cells was studied. The removal effect of the N layer and antireflection coating (ARC) of the waste solar cell were investigated at room temperature ($25^{\circ}C$) by variation of concentration of $H_3PO_4$, $NH_4HF_2$, and concentration and types of chelating agent. Removal efficiency was the best in the conditions; 10 wt% $H_3PO_4$ 2.0 wt% $NH_4HF_2$, 1.5 wt% Hydantoin. Increasing the concentration of $H_3PO_4$, the surface contamination degree was increased and the thickness of the silicon wafe became thicker than the thickness before surface treatment because of re-adsorption on the silicon wafer surface by electrostatic attraction of the fine particles changed to (+). The etching method by mixed solution of $H_3PO_4$-$NH_4HF_2$-chelating agents was expected to be great as an alternative to conventional RCA cleaning methods and as the recycle method of waste solar cells, because all processes are performed at room temperature, the process is simple, and less wastewater, the removal efficiency of the surface of the solar cell was excellent.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Journal of Adhesion and Interface
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• v.21 no.4
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• pp.143-155
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• 2020

Hydrophobic Organic-Inorganic (O-I) hybrid materials prepared by sol-gel process have been widely used at functional coating fields such as coatings for anti-corrosion, anti-icing, self-cleaning, anti-reflection. The key point for fabricating hydrophobic surface is to optimize the surface energy and roughness of the coating films. There are typical processes to control the surface energy and roughness which are 'In situ fabricating', 'Pre-fluorinating/Post-roughening', 'Pre-roughening/ Post-fluorinating'. In this study, particle-binder process was used for in-situ fabrication of hydrophobic coating films. Various O-I hybrid compounds prepared using several kinds of alkoxysilane compounds were used as a binder for silica nanoparticles at particle-binder process. To study effect of fluorine content and weight ratio of particle : binder on the hydrophobicity and surface morphology, Hydrophobic coating films were prepared onto glass substrate at various content of fluorine content of O-I hybrid binder and weight ratio of particle : binder. The coating films prepared using O-I hybrid binder (GPTi-HF10) having 10 wt% of fluorine content showed the highes water contact angle (107.52±1.6°). The coating films prepared at 1:3 weight ratio of GPTi-HF10 : silica nanoparticle exhibited the highest water contact angle (130.84±1.99°).