• Journal of Broadcast Engineering
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• v.17 no.2
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• pp.325-343
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• 2012

This paper proposes the coding method to predict the split structure of LCU in the current frame on the basis of the reference frame or temporally-previous frame. HEVC encoder determines split structure according to image characteristics in LCU which is an basic element of CU. The split structure of the current LCU is very similar to the split structure of collocated LCU in the reference frame or temporally-previous frame. Thus, this paper proposes the method to reduce the encoder computational complexity by predicting split structure of the current LCU on the basis of that of collocated LCU in the reference frame or temporally-previous frame. And it also proposes the method to reduce the BD-Bitrate by coding after the prediction of the CU split information. The simulation results of changing only encoder showed that the mean of encoder computational complexity was lower by 21.3%, the decoder computational complexity was negligible change and the BD-Bitrate increase by the maximum of 0.6%. Also, the method changing encoder, bitstream, and decoder improves the mean of encoder computational complexity was lower by 22%, the decoder computational complexity was negligible change and the BD-Bitrate is improved to the maximum of 0.3%. When compared with the conventional method, indicating that the proposed method is superior.

• Smart Media Journal
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• v.1 no.2
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• pp.6-11
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• 2012

In the HEVC standard, transform coefficient coding that affects the output bitstream directly is a core part of the encoder and it includes coefficient scanning and entropy coding. Recently, JCT-VC(Joint Collaborative Team on Video Coding) advances to HEVC Committee Draft (CD). In this paper, we explain HEVC transform coefficient coding and propose an efficient transform coefficient coding method considering statistics of transform coefficients in the intra frame coder. The proposed method reduces BD-Rate by up to 0.74%, compared to the conventional HEVC transform coefficient coding.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.129-138
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• 2014

This paper proposes a fast intra prediction method to reduce encoding time for the HEVC(high-efficiency video coding) encoder. The proposed fast Intra prediction method uses quadtree structure and SATD(Sum of Absolute Transformed Differences). In HEVC, a $8{\times}8$ SATD value using $8{\times}8$ hadamard transform is used to calculate a SATD value for $8{\times}8$ or larger blocks. The proposed method calculates the best SATD value by using each $8{\times}8$ SATD result in $16{\times}16$ or larger blocks. After that, the proposed method removes a candidate mode for RDO(Rate-Distortion Optimization) based on comparing SATD of the candidate mode and the best SATD. By removing candidate modes, the proposed method reduces the operation of RDO and reduces total encoding time. In $8{\times}8$ block, the proposed method uses additional $4{\times}4$ SATD to calculat the best SATD. The experimental results show that the proposed method achieved 5.08% reduction in encoding time compared to the HEVC test model 12.1 encoder with almost no loss in compression performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.767-773
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• 2017

In this paper, we propose a design of Intra prediction angular mode decision for HEVC encoder. Intra prediction coding of HEVC is a method for predicting a current block by referring to samples reconstructed around a current block. Intra prediction supports a total of 35 modes with 1 DC mode, 1 Planar mode, and 33 Angular modes. Intra prediction coding of HEVC works by performing all 35 modes for efficient encoding. However, in order to process all of the 35 modes, the computational complexity and operational time required are high. Therefore, this paper proposes comparing the difference in the value of the original pixel, using an algorithm that determines angular mode efficiently. This new algorithm reduces the Hardware size. The hardware which is proposed was designed using Verilog HDL and was implemented in 65nm technology. Its gate count is 14.9K and operating speed is 2GHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.397-400
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• 2016

In this paper, we propose an efficient algorithm for computing architecture for high-performance Inter Prediction SAD HEVC encoder. HEVC Motion Estimation (ME) of the Inter Prediction is a process for searching for the currently high prediction block PU and the correlation in the interpolated reference picture in order to remove temporal redundancy. ME algorithm uses full search(FS) or fast search algorithm. Full search technique has the guaranteed optimal results but has many disadvantages which include high calculation and operational time due to the motion prediction with respect to all candidate blocks in a given search area. Therefore, this paper proposes a new algorithm which reduces the computational complexity by reusing the SAD operation in full search to reduce the amount of calculation and computational time of the Inter Prediction. The proposed algorithm is applied to an HEVC standard software HM16.12. There was an improved operational time of 61% compared to the traditional full search algorithm, BDBitrate was decreased by 11.81% and BDPSNR increased by about 0.5%.

• ETRI Journal
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• v.35 no.2
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• pp.270-280
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• 2013

A fast intra-prediction method is proposed for High Efficiency Video Coding (HEVC) using a fast intra-mode decision and fast coding unit (CU) size decision. HEVC supports very sophisticated intra modes and a recursive quadtree-based CU structure. To provide a high coding efficiency, the mode and CU size are selected in a rate-distortion optimized manner. This causes a high computational complexity in the encoder, and, for practical applications, the complexity should be significantly reduced. In this paper, among the many predefined modes, the intra-prediction mode is chosen without rate-distortion optimization processes, instead using the difference between the minimum and second minimum of the rate-distortion cost estimation based on the Hadamard transform. The experiment results show that the proposed method achieves a 49.04% reduction in the intra-prediction time and a 32.74% reduction in the total encoding time with a nearly similar coding performance to that of HEVC test model 2.1.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.145-148
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• 2016

In this paper, we propose a design of Intra Prediction angular mode decision for high-performance HEVC encoder. Intra Prediction works by performing all 35 modes for efficient encoding. However, in order to process all of the 35 modes, the computational complexity and operational time required are high. Therefore, this paper proposes comparing the difference in the value of the original image pixel, using an algorithm that determines Angular mode efficiently. This new algorithm reduces the Hardware size. The hardware which is proposed was designed using Verilog HDL and was implemented in 65nm technology. Its gate count is 14.9k and operating speed is 2GHz.

• Journal of Broadcast Engineering
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• v.18 no.5
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• pp.691-701
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• 2013

In this paper, an early termination algorithm for merge process is proposed to reduce the computational complexity in High Efficiency Video Coding (HEVC) encoder. In the HEVC, the same candidate modes from merge candidate list (MCL) are shared to predict a merge or merge SKIP mode. This search process is performed by the number of the obtained candidates for the both of the merge and SKIP modes. This may cause some redundant search operations. To reduce this redundant search operation, we employ the neighboring blocks which have been encoded in prior, to check on the contextual information. In this study, the spatial, temporal and depth neighboring blocks have been considered to compute a correlation information. With this correlation information, an early termination algorithm for merge process is suggested. When all modes of neighboring blocks are SKIP modes, then the merge process performs only SKIP mode. Otherwise, usual merge process of HEVC is performed Through experimental results, the proposed method achieves a time-saving factor of about 21.25% on average with small loss of BD-rate, when comparing to the original HM 10.0 encoder.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.169-177
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• 2015

This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.755-758
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• 2014

In this paper, we propose effective Deblocking Filter hardware architecture for High Efficiency Video Coding encoder. we propose Deblocking Filter hardware architecture with less processing time, filter ordering for low area design, effective memory architecture and four-pipeline for a high performance HEVC(High Efficiency Video Coding) encoder. Proposed filter ordering can be used to reduce delay according to preprocessing. It can be used for realtime single-port SRAM read and write. it can be used in parallel processing by using two filters. Using 10 memory is effective for solving the hazard caused by a single-port SRAM. Also the proposed filter can be used in low-voltage design by using clock gating architecture in 4-pipeline. The proposed Deblocking Filter encoder architecture is designed by Verilog HDL, and implemented by 100k logic gates in TSMC $0.18{\mu}m$ process. At 150MHz, the proposed Deblocking Filter encoder can support 4K Ultra HD video encoding at 30fps, and can be operated at a maximum speed of 200MHz.