• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.350-353
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• 2007

This paper presents an real-time implementation of H.264/AVC High 4:4:4 Predictive profile decoder using general-purpose processors by exploiting multi-threading technique and Single Instruction Multiple Data (SIMD) instructions without any quality degradation. We analyze differences between the existing High profile and High 4:4:4 Predictive profile decoder, and show various optimization techniques to decode high fidelity and high definition (HD) video in real-time. Simulation results show that the proposed decoder can play high fidelity HD video at average 40 frames per seconds (fps) for the IBBrBP bistream and about 50 fps for the Intra-only bitstream.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.142-147
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• 2009

The recent H.264/AVC video coding standard provides a higher coding efficiency than previous standards. H.264/AVC achieves a bit rate saving of more than 50 % with many new technologies, but it is computationally complex. Most of fast mode decision algorithms have focused on Baseline profile of H.264/AVC. In this paper, a fast block mode decision scheme for P- slices in High profile is proposed to reduce the computational complexity for H.264/AVC because the High profile is useful for broadcasting and storage applications. To reduce the block mode decision complexity in P- pictures of High profile, we use the SAD value after $16{\times}16$ block motion estimation. This SAD value is used for the classification feature to divide all block modes into some proper candidate block modes. The proposed algorithm shows average speed-up factors of 47.42 ${\sim}$ 67.04% for IPPP sequences.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.112-115
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• 2008

In this paper, we propose H.264 High Profile Encoder Intra Prediction module. This designed module can be operated in 306 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 13.2 and verified the our developed hardware using test vector generated by reference C. We adopt plan removal and SAD calculation to reduce the Hardware cost and cycle. The designed circuit can be operated in 133MHz clock system, and has 250K gate counts using TSMC 0.18um process including SRAM memory.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2045-2049
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• 2008

In this paper, we propose an novel architecture for H.264 High Profile Encoder Intra Prediction module. This designed module can be operated in 306 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 13.2 and verified the our developed hardware using test vector generated by reference C. We adopt plan removal and SAD calculation to reduce the Hardware cost and cycle. The designed circuit can be operated in 133MHz clock system, and has 250K gate counts using TSMC 0.18 um process including SRAM memory.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2285-2291
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• 2011

In this paper, H.264 high profile intra frame encoder, which integrates intra prediction, context-based adaptive variable length coding(CAVLC), and DDR2 memory control module, is proposed. The designed encoder can be operated in 440 cycle for one-macroblock. In order to verify the encoder function, we developed the reference C from JM 13.2 and verified the developed hardware using test vector generated by reference C. The designed encoder is verified in the FPGA (field programmable gate array) with operating frequency of 200 MHz for DMA (direct memory access), operating frequency of 50 MHz of Encoder module, and 25 MHz for VIM(video input module). The number of LUT is 43099, which is about 20 % of Virtex 5 XC5VLX330.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.1
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• pp.110-116
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• 2009

It is very important for a DVR system to compress mass video data because they should be able to store#playback of video data. There are several high efficient DVR products using ordinary MPEG-4 compression fur data compression. But most of them support only CIF(D1/4) image, which means degraded image quality in comparison with input image source. In this paper, M-JPEG and H.264 Codec are realized using DSP. To multiple channels system M-JPEG is used for data transmission through network, and Data compression rate is improved as about 4 times as ordinary MPEG-4 compression by supporting Baseline Profile of H.264. As a result, high resolution with the width 720 pixels and the height 480 pixels can be supported.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.639-642
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• 2005

In this paper, we assessed the subjective and objective quality of the images on low bit-rate which used the H.264 intra coding and JPEG2000. The result of our experiments shown the subjective and objective quality assessment of the intra coded image of H.264 high profile is better than JPEG2000. But, the blocking artifact is obvious because of the big difference of DCT and wavelet transform and quantization. it will be necessary to propose a new transform algorithm for the optimal quality.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.203-216
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• 2004

Recent advances in video coding technology have resulted in rapid growth of application in mobile communication, With this explosive growth reliable transmission and error resilient technique become increasingly necessary to offer high quality multimedia service. In this paper, we present the result of our investigation on the error resilient performance evaluation of the MPEG-4 simple profile under the H.324/M and the H.264/AVC baseline under the IP packet networks. Especially, we have tested error resilient tools of MPEG-4 simple profile such as resynchronization marker insertion, data partitioning, and of H.264/AVC baseline such as the flexible macroblock ordering (FMO) scheme. The objective quality of decoded video is measured in terms of rate and PSNR under various random bit and burst error conditions.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.6 s.312
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• pp.97-104
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• 2006

The state-of-the-art H.264/AVC standard was designed for the lossy video coding so that it could not yield the best performance for lossless video coding. In this paper, we propose two efficient intra lossless coding methods by embedding a pixel-wise prediction into the H.264/AVC. One is based on the pixel-wise prediction for the residual signal of the H.264/AVC intra Prediction and the other suggests a newly additional intra prediction mode for the conventional intra prediction. We found that the proposed lossless coding algorithms could achieve approximately $12%{\sim}25%$ more bit saving compared to the H.264/AVC FRExt high profile for several test sequences in terms of a compression ratio.

• ETRI Journal
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• v.31 no.6
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• pp.784-794
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• 2009

We present a full HD (1080p) H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external memory access to fetch samples, which degrades the performance of the encoder. A novel approach to fast ME which uses shared multibank memory can solve these problems. The proposed pixel subsampling ME algorithm is suitable for fast motion vector searches for high-quality resolution images. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software, while sustaining the video quality without any conspicuous PSNR loss. The usage amount of shared multibank memory between the coarse ME and fine ME blocks is 93.6%, which saves external memory access cycles and speeds up ME. It is feasible to perform the algorithm at a 270 MHz clock speed for 30 frame/s real-time full HD encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.