• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.102-111
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.

• ETRI Journal
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• v.29 no.3
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• pp.396-398
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• 2007

This letter presents an architecture based on a new double-filter strategy to perform the adaptive in-loop filtering process specified by the H.264/AVC standard. The proposed architecture shows considerable advantages, both in terms of hardware cost and latency, when compared with the approaches found in the most recent literature.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06b
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• pp.464-468
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• 2008

본 논문은, H,264/AVC 비디오 코덱의 저전력용 CAVLC 디코더를 위한 coeff_token 회로의 면적을 최적화 한 설계를 제시한다. CAVLC 디코더의 전력 소비를 줄이기 위해서 coeff_token 회로에서의 메모리 참조 빈도수를 줄이는 여러 가지 방법이 제안되어 왔다. 본 논문에서는 기존의 저전력용으로 개발된 coeff_token 회로 중 가장 전력 소비가 낮은 방식의 메모리 구조와 수식 계산 회로를 변형시켜서 전력 소비를 같은 수준으로 유지하면서도 면적을 더욱 줄이는 방법을 제안한다. 본 연구결과를 삼성 0.18 um 공정을 대상으로 합성한 결과 기존 방식에 비해서 1.1% 면적이 줄어드는 성과를 거두었다.

• Proceedings of the KAIS Fall Conference
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• 2011.12b
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• pp.434-437
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• 2011

본 논문에서는 H.264/AVC 복호기의 성능을 향상시키기 위해 병렬 역양자화 구조와 역변환 구조를 제안한다. 제안하는 역양자화 구조는 공통 연산기를 사용하여 계산 복잡도를 감소시키고, 4개의 공통연산기를 사용하여 역양자화 수행 사이클 수를 1 사이클로 감소시킨다. 제안하는 역변환 구조는 4개의 변환 연산기를 사용하여 역변환 연산을 수행하는데 2 사이클이 소요된다. 또한 제안하는 구조는 역양자화 연산과 수평 역변환 연산을 동시에 수행하는 병렬 구조를 채택하여 역양자화 및 역변환 수행 사이클 수를 2 사이클로 감소시킨다. 제안하는 구조를 Magnachip 0.18um CMOS 공정 라이브러리를 이용하여 합성한 결과 1.5MHz의 동작 주파수에서 게이트 수는 14,173이고, 표준 참조 소프트웨어 JM 9.4에서 추출한 데이터를 이용하여 성능을 측정한 결과 제안하는 구조의 수행 사이클 수가 기존 구조 대비 38.74% 향상되었다.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06d
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• pp.555-559
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• 2007

국제 비디오 압축 표준인 H.264/AVC는 MPEG-2나 MPEG-4등에 비해 압축률이 2배 이상 향상되어 저대역폭을 가지는 모바일 단말기 기반의 네트워크에서도 이전의 압축표준보다 훨씬 좋은 품질의 영상을 제공하나 높아진 압축률에 상응하여 복잡도 또한 증가하였다. 이러한 복잡도를 해결하기 위하여 디코딩을 하는 과정에서 병목현상을 일으키는 부분들을 하드웨어의 최적화된 설계로 해결해왔다. 이러한 하드웨어 기반 해결은 단말기의 교체라는 단점을 가지고 있다. 이러한 단점을 해결하기 위하여 본 논문에서는 소프트웨어 디코더가 모바일 단말기에 적용되기 위한 조건들을 살펴보고 디코딩 과정 중에 가장 많은 병목 현상을 가지는 디블록킹 필터(De-Blocking Filter)를 모바일 단말기에 적용하기 위한 방법을 제안한다. 이러한 시도는 모바일 단말기 상에서 하드웨어 기반 디코더가 아닌 소프트웨어 기반 디코더가 구현 될 수 있는 기초가 된다.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.292-294
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• 2007

Recently, for satisfying many application demands such as coding delay, computing power, transporting channel characteristic, etc, many profiles are supported in video coding standards. Therefore, in transcoding between same standards or between other standards, the functional difference of profiles supported by application occur many problems. In this paper, transcoding MPEG-2 main profile to H.264/AVC baseline profile which has restriction in the number of reference frame is focused. In this case, the bidirectional prediction supported in MPEG-2 main profile is not supported in H.264/AVC baseline profile. Also, in the restriction of reference frame, motion vectors in the MPEG-2 decoder as predictor should be adjusted. In this paper, the proposed algorithm is based on the characteristic of which motion. vector is uniform according to the distance from reference frame. The adaptive search techniques through the determination of the uniformity extremely reduce the computational complexity.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06a
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• pp.247-249
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• 2006

본 논문에서는 임베디드 리눅스와 그에 따른 통합 개발 환경인 QpusME/Esto에서 제공하는 전력소모량 분석도구를 이용하여 H.264 디코더의 함수별 전력 소모량을 측정하여 공개함으로써 향후 연구에 기반 정보로 사용하도록 한다. 또한 이를 이용하여 MacroBlock 디코딩시, 전력을 줄일 수 있는 다양한 방법 중 하나의 예를 제시하고 그 실험 결과를 제시한다.

• Journal of information and communication convergence engineering
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• v.11 no.1
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• pp.50-55
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• 2013

In this paper, we propose a parallel intra-operation unit and a memory architecture for improving the performance of intra-prediction, which utilizes spatial correlation in an image to predict the blocks and contains 17 prediction modes in total. The design is targeted for portable devices applying H.264/AVC decoders. For boosting the performance of the proposed design, we adopt a parallel intra-operation unit that can achieve the prediction of 16 neighboring pixels at the same time. In the best case, it can achieve the computation of one luma $16{\times}16$ block within 16 cycles. For one luma $4{\times}4$ block, a mere one cycle is needed to finish the process of computation. Compared with the previous designs, the average cycle reduction rate is 78.01%, and the gate count is slightly reduced. The design is synthesized with the MagnaChip $0.18{mu}m$ library and can run at 125 MHz.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.1
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• pp.90-102
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• 2011

Recently, the grade of users using wireless communication services which transmits and re-transmits to the signal via the broadcasting satellite have a variety. However the ships not preparing of H.264 standard devices should not received the realtime data because the broadcasting stations have transmitted the compressed video data through the satellite communication. Therefore this paper proposes H.264 to MPEG-2 transcoding for the ships using MPEG-2 devices. Proposed method improves a speed and object quality in H.264 to MPEG-2 transcoding by analysis features of macroblock modes in H.264. In the Intra mode of P-frame, it proposes new method by computing coincidence proportion after comparing of Intra mode methods of H.264 and MPEG-2. In the Inter mode, it proposes a PMV(predictive motion vector) considering movement of motion vectors in H.264 decoder. we reuses a PMV directly as like the final MV in MPEG-2 encoder and refinements the MV after coincidence ratio comparing of variable motion vectors of H.264 and these of MPEG-2. The experimental results from proposed method show a considerable reduction in processing time, as much as 70% and 67% respectively, with a small objective quality reduction in PSNR.

• Journal of Broadcast Engineering
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• v.16 no.1
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• pp.133-143
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• 2011

In this paper, a complexity-balancing algorithm is proposed for distributed video coding based on entropy coding. In order to reduce complexity of DVC-based decoders, the proposed method employs an entropy coder instead of channel coders and the complexity-balancing method is designed to improve RD performance with minimal computational complexity. The proposed method performs motion estimation in the decoder side and transmits the estimated motion vectors to the encoder. The proposed encoder can perform more accurate refinement using the transmitted motion vectors from the decoder. During the motion refinement, the optimal predicted motion vectors are decided by the received motion vector and the predicted motion vectors and complexity load of block is allocated by adjusting the search range based on the difference between the received motion vector and the predicted motion vectors. The computational complexity of the proposed encoder is decreased 11.9% compared to the H.264/AVC encoder and that of the proposed decoder are reduced 99% compared to the conventional DVC decoder.