• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.3
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• pp.142-148
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• 2008

Though a deblocking filter of H.264/AVC provides enhanced image quality by removing blocking artifact on block boundary, the complex filtering operation on this process is a dominant factor of the whole decoding time. In this paper, we designed an ASIP to accelerate deblocking filter operation with the proposed instruction set. We designed a processor based on a MIPS structure with LISA, simulated a deblocking later model, and compared the execution time on the proposed instruction set. In addition, we generated HDL model of the processor through CoWare's Processor Designer and synthesized with TSMC 0.25um CMOS cell library by Synopsys Design Compiler. As the result of the synthesis, the area and delay time increased 7.5% and 3.2%, respectively. However, due to the proposed instruction set, total execution performance is improved by 18.18% on average.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2253-2260
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• 2012

In this paper, an efficient hardware architecture is proposed for inverse transform and inverse quantization of H.264/AVC decoder. The previous inverse transform and quantization architecture has a different AC and DC coefficients decoding order. In the proposed architecture, IQ is achieved after IT regardless of the DC or AC coefficients. A common operation unit is also proposed to reduce the computational complexity of inverse quantization. Since division operation is included in the previous architecture, it will generate errors if the processing order is changed. In order to solve the problem, the division operation is achieved after IT to prevent errors in the proposed architecture. The architecture is implemented with 3-stage pipeline and a parallel vertical and horizontal IDCT is also implemented to reduce the operation cycle. As a result of analyzing the proposed ITIQ architecture operation cycle for one macroblock, the proposed one has improved by 45% than the previous one.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.77-82
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• 2008

H.264 is a video coding standard of ITU-T and ISO/IEC, and widely spreads its application due to its high compression ratio more than twice that of MPEG-2 and high image quality. It has different architecture depending on demands since it is a lied from small image of QVGA to large size of HD. In this paper, We propose a scalable architecture for intra-prediction of H.264 decoders. The proposed scheme has a scalable architecture that can accommodate up to 4 processing elements depending on performance demands and can reduce the number of access to memory using efficient memory management so as to be energy-efficient. We design the intra-prediction unit using Verilog-HDL and verily it by prototyping using an FPGA. The performance is analyzed using the results of design.

• Journal of Broadcast Engineering
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• v.15 no.4
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• pp.540-546
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• 2010

Since the stereoscopic 3-dimensional (3D) video that provides users with a realistic multimedia service requires twice as much data as 2-dimensional (2D) video, it is difficult to construct the fast system. In this paper, we propose a fast stereoscopic 3D broadcasting system based on the depth information. Before the transmission, we encode the input 2D+depth video using x264, an open source H.264/AVC fast encoder to reduce the size of the data. At the receiver, we decode the transmitted bitstream in real time using a compute unified device architecture (CUDA) video decoder API on NVIDIA graphics processing unit (GPU). Then, we apply a fast view synthesis method that generates the virtual view using GPU. The proposed system can display the output video in both 2DTV and 3DTV. From the experiment, we verified that the proposed system can service the stereoscopic 3D contents in 24 frames per second at most.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.35-43
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• 2008

A new effective parallel decoding method has been developed for context-based adaptive variable length codes. In this paper, several new design ideas have been devised for scalable parallel processing, less area, and less power. First, simplified logical operations instead of memory look-ups are used for fast low power operations. Second the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of input are simultaneously analyzed. For comparison, we have designed the logical operation based parallel decoder for M=8 and a typical conventional method based decoder. High speed parallel decoding is possible with our method. For similar decoding rates (1.57codes/cycle for M=8), our new approach uses 46% less area than the typical conventional method.

• Proceedings of the Korea Contents Association Conference
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• 2006.11a
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• pp.499-502
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• 2006

H.264/MPEG4 Advanced Video coding joint standard needs deblocking filter of decoder. We propose a better deblocking algorithm ensuring picture quality even if it is low bit-rate and bandwidth in MPEG-4 video. The complexity diminishes in proposed deblocking algorithm because it uses only simple shift, addition and comparison. We handle dividing into complexity area, medium area and simple area after counting boundary intensity of mask block to identify presence of block effects. As a result of experiment, we make certain of that block effects reduces in proposed deblocking algorithm.

• The KIPS Transactions:PartA
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• v.15A no.1
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• pp.61-68
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• 2008

In this paper, we propose the VLSI design of Multi-Format Video Decoder (MFD) to support video codec standards such as MPEG-2, MPEG-4, H.264 and VC-1. The target of the proposed MFD is the Full HD (High Definition) video processing needed for the high-end D-TV SoC (System-on-Chip). The size of the design is reduced by sharing the common large-size resources such as the RISC processor and the on-chip memory among the different codecs. In addition, a detachable architecture is introduced in order to easily add or remove the codecs. The detachable architecture preserves the stability of the previously designed and verified codecs. The size of the design is about 2.4 M gates and the operating clock frequency is 225MHz in the Samsung 65nm process. The proposed MFD supports more than Full-HD (1080p@30fps) video decoding, and the largest number of video codec standards known so far.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.11a
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• pp.138-139
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• 2010

본 논문은 저복잡도 비디오 부/복호화를 위한 엔트로피 부호화 기반의 분산 비디오 코딩 방법을 제안한다. 제안하는 엔트로피 부호화 기반의 분산 비디오 코딩은 복호기의 복잡도를 줄이기 위하여 기존의 분산 비디오 코딩에서 사용하는 채널코딩을 이용하는 것이 아니라 엔트로피 코딩을 이용하여 부호화를 수행한다. 제안하는 방법에서 복호가는 움집임 추정을 수행하고 그 결과인 움직임 백터를 부호기로 전송하며, 부호기는 전송받은 움직임 백터를 초기 움직임 백터로 하여 움직임 백터 값의 갱신을 수행한다. 제안한 방법의 성능을 평가하기 위하여 기존의 분산 비디오 코딩 방법과 복호기 복잡도를 비교한 결과 99%의 복잡도 감소가 있었고, H.264/AVC의 All Intra 방법과 비교하여 20.3%의 비트율 감소가 있었다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.11a
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• pp.229-231
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• 2011

H.264/AVC와 같은 동영상 압축 기술은 동영상의 압축에 필요한 연산이 대부분 부호기에서 이루어진다. 반면에 분산 동영상 압축 기법은 정보 압축에 필요한 연산이 대부분 복호기에서 수행되는 구조를 가진다. 본 논문에서는 분산 동영상 압축 기법의 구성 요소 중 오류 정정 부호기와 복호기에 사용되는 오류 정정 부호 중 LDPC 부호의 성능을 향상 시킬 수 있는 새로운 복호 기법을 제안한다. 제안하는 기법을 적용하여 추가적인 연산 없이 LDPC 부호의 오류 정정 성능을 향상시킬 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.71-78
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• 2008

In this paper, we implement the H.264/AVC baseline decoder by hardware-software partitioning under the embedded Linux Kernel 2.4.26 and the FPGA-based target board with ARM926EJ-S core. We design several IPs for the time-demanding blocks, such as motion compensation, deblocking filter, and YUV-to-RGB and they are communicated with the host through the AMBA bus protocol. We also try to minimize the number of memory accesses between IPs and the reference software (JM 11.0) which is ported in the embedded Linux. The proposed IPs and the system have been designed and verified in several stages. The proposed system decodes the QCIF sample video at 2 frame per second when 24MHz of system clock is running and we expect the bitter performance if the proposed system is designed with ASIC.