• Title/Summary/Keyword: Guaranteed scheduling

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Smoothing DRR: A fair scheduler and a regulator at the same time (Smoothing DRR: 스케줄링과 레귤레이션을 동시에 수행하는 서버)

  • Joung, Jinoo
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.19 no.1
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    • pp.63-68
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    • 2019
  • Emerging applications such as Smart factory, in-car network, wide area power network require strict bounds on the end-to-end network delays. Flow-based scheduler in traditional Integrated Services (IntServ) architecture could be possible solution, yet its complexity prohibits practical implementation. Sub-optimal class-based scheduler cannot provide guaranteed delay since the burst increases rapidly as nodes are passed by. Therefore a leaky-bucket type regulator placed next to the scheduler is being considered widely. This paper proposes a simple server that achieves both fair scheduling and traffic regulation at the same time. The performance of the proposed server is investigated, and it is shown that a few msec delay bound can be achieved even in large scale networks.

Antenna Selection Algorithm for Energy Consumption Minimization in Massive Antenna System (다중안테나 시스템에서 전력 최소화를 위한 안테나 선택 알고리즘)

  • Shin, Kyung-Seop
    • Journal of Convergence for Information Technology
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    • v.12 no.3
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    • pp.280-285
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    • 2022
  • In order to ensure maximum capacity at a given frequency resource, the number of antennas must be increased. The increase in antennas means that such guaranteed channel resources can be used as an increase in channel capacity by aquiring another channel resource. In order to aggregate antennas in such a situation where there are a plurality of antennas, a problem of miniaturizing and integrating antennas must be accompanied. In this situation, in order to efficiently allocate channel resources and antenna resources in limited device resources, the problem of antenna selection and user scheduling was considered and solved together. By numerical simulation results, the proposed algorithm was proven to effectively reduce 34 % power consumption in averagewith increase in antennas.

Two-Way Donation Locking for Transaction Management in Distributed Database Systems (분산환경에서 거래관리를 위한 두단계 기부 잠금규약)

  • Rhee, Hae-Kyung;Kim, Ung-Mo
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.12
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    • pp.3447-3455
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    • 1999
  • Database correctness is guaranteed by standard transaction scheduling schemes like two-phase locking for the context of concurrent execution environment in which short-lived ones are normally mixed with long-lived ones. Traditional syntax-oriented serializability notions are considered to be not enough to handle in particular various types of transaction in terms of duration of execution. To deal with this situation, altruistic locking has attempted to reduce delay effect associated with lock release moment by use of the idea of donation. An improved form of altruism has also been deployed in extended altruistic locking in a way that scope of data to be early released is enlarged to include even data initially not intended to be donated. In this paper, we first of all investigated limitations inherent in both altruistic schemes from the perspective of alleviating starvation occasions for transactions in particular of short-lived nature. The idea of two-way donation locking(2DL) has then been experimented to see the effect of more than single donation in distributed database systems. Simulation experiments shows that 2DL outperforms the conventional two-phase locking in terms of the degree of concurrency and average transaction waiting time under the circumstances that the size of long-transaction is in between 5 and 9.

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A Lower Bound Estimation on the Number of Micro-Registers in Time-Multiplexed FPGA Synthesis (시분할 FPGA 합성에서 마이크로 레지스터 개수에 대한 하한 추정 기법)

  • 엄성용
    • Journal of KIISE:Computer Systems and Theory
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    • v.30 no.9
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    • pp.512-522
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    • 2003
  • For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Typically, the size of the chip required to implement the circuit depends on both the maximum number of the LUT blocks required to implement the function of each subcircuit and the maximum number of micro-registers to store results over context switches in the same time. Therefore, many partitioning or synthesis methods try to minimize these two factors. In this paper, we present a new estimation technique to find the lower bound on the number of micro-registers which can be obtained by any synthesis methods, respectively, without performing any actual synthesis and/or design space exploration. The lower bound estimation is very important in sense that it greatly helps to evaluate the results of the previous work and even the future work. If the estimated lower bound exactly matches the actual number in the actual design result, we can say that the result is guaranteed to be optimal. In contrast, if they do not match, the following two cases are expected: we might estimate a better (more exact) lower bound or we find a new synthesis result better than those of the previous work. Our experimental results show that there are some differences between the numbers of micro-registers and our estimated lower bounds. One reason for these differences seems that our estimation tries to estimate the result with the minimum micro-registers among all the possible candidates, regardless of usage of other resources such as LUTs, while the previous work takes into account both LUTs and micro-registers. In addition, it implies that our method may have some limitation on exact estimation due to the complexity of the problem itself in sense that it is much more complicated than LUT estimation and thus needs more improvement, and/or there may exist some other synthesis results better than those of the previous work.

Design and Implementation of Transmission Scheduler for Terrestrial UHD Contents (지상파 UHD 콘텐츠 전송 스케줄러 설계 및 구현)

  • Paik, Jong-Ho;Seo, Minjae;Yu, Kyung-A
    • Journal of Broadcast Engineering
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    • v.24 no.1
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    • pp.118-131
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    • 2019
  • In order to provide 8K UHD contents of terrestrial broadcasting with a large capacity, the terrestrial broadcasting system has various problems such as limited bandwidth and so on. To solve these problems, UHD contents transmission technology has been actively studied, and an 8K UHD broadcasting system using terrestrial broadcasting network and communication network has been proposed. The proposed technique is to solve the limited bandwidth problem of terrestrial broadcasting network by segmenting 8K UHD contents and transmitting them to heterogeneous networks through hierarchical separation. Through the terrestrial broadcasting network, the base layer corresponding to FHD and the additional enhancement layer data for 4K UHD are transmitted, and the additional enhancement layer data corresponding to 8K UHD is transmitted through the communication network. When 8K UHD contents are provided in such a way, user can receive up to 4K UHD broadcasting by terrestrial channels, and also can receive up to 8K UHD additional communication networks. However, in order to transmit the 4K UHD contents within the allocated bit rate of the domestic terrestrial UHD broadcasting, the compression rate is increased, so a certain level of image deterioration occurs inevitably. Due to the nature of UHD contents, video quality should be considered as a top priority over other factors, so that video quality should be guaranteed even within a limited bit rate. This requires packet scheduling of content generators in the broadcasting system. Since the multiplexer sends out the packets received from the content generator in order, it is very important to make the transmission time and the transmission rate of the process from the content generator to the multiplexer constant and accurate. Therefore, we propose a variable transmission scheduler between the content generator and the multiplexer to guarantee the image quality of a certain level of UHD contents in this paper.