• Title/Summary/Keyword: Graphic processor

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A study on DSP based power analyzing and control system by analysis of 3-dimensional space current co-ordinates (3차원 전류좌표계 해석법에 의한 DSP 전력분석 제어장치에 관한 연구)

  • 임영철;정영국;나석환;최찬학;장영학;양승학
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.45 no.4
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    • pp.543-552
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    • 1996
  • The goal of this paper is to developed a DSP based power analyzing and control system by 3-Dimensional (3-D) space current co-ordinates. A developed system is made up of 486-PC and DSP (Digital Signal Processor) board, Active Power Filter, Non-linear thyristor load, and Power analyzing and control program for Windows. Power is analyzed using signal processing techniques based on the correlation between voltage and current waveforms. Since power analysis algorithm is performed by DSP, power analysis is achieved in real-time even under highly dynamic nonlinear loading conditions. Combining control algorithm with power analysis algorithm is performed by DSP, power analysis is achieved in real-time even under highly dynamic nonlinear loading conditions. Combining control algorithm with power analysis algorithm, flexibility of the proposed system which has both power analysis mode and control mode, is greatly enhanced. Non-active power generated while speed of induction motor is controlled by modulating firing angle of thyristor converter, is compensated by Active Power Filter for verifying a developed system. Power analysis results, before/after compensation, are numerically obtained and evaluated. From these results, various graphic screens for time/frequency/3-D current co-ordinate system are displayed on PC. By real-time analysis of power using a developed system, power quality is evaluated, and compared with that of conventional current co-ordinate system. (author). refs., figs. tabs.

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Development of Data Acquistion and Processing System for the Analysis of Biophysiological signal (생체신호 처리를 위한 시스템 개발)

  • 이준하;이상학;신현진
    • Progress in Medical Physics
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    • v.3 no.1
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    • pp.71-78
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    • 1992
  • This study describes the design of the biophysiological signal processing analyzer which can collect and analyze the biosignal raw data. System hardware is consisted of the IBM PC AT. pre-amplifier. AID converter, Counter/Timer. and RS-232C processor. Biophysiological signal data were processed by the software digital filter. FFT and graphic processing routine. The tachogram and FFT of the the peak to peak interval time was accomplished by the Graphic user interface software using the biophysiological signal processed data. Using this system. the powerspectrum of the heart rate variability during the long term could be observed. Experimental results of this system approach our purpose. which is improved the cost performance. easy to use. reducing raw-data noise and optimizing model for digital filter.

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An Efficient 2-dimensional Addressing Mode for Image Processor (영상처리용 프로세서를 위한 효율적인 이차원 어드레스 지정 기법)

  • Go, Yun-Ho;Yun, Byeong-Ju;Kim, Seong-Dae
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.38 no.5
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    • pp.486-497
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    • 2001
  • In this paper, we propose a new addressing mode, which can be used for programmable image processor to perform image-processing algorithms effectively. Conventional addressing modes are suitable for one-dimensional data processing such as voice, but the proposed addressing mode consider two-dimensional characteristics of image data. The proposed instruction for two-dimensional addressing requires two operands to specify a pixel and doesn't require any change of memory architecture. The proposed two-dimensional addressing mode for image processor has the following advantages. The proposed instruction combines several instructions to load a pixel data from an external memory to a register. Hence, the proposed instruction reduces required code size so that it satisfies high performance and low power requirements of image processor. In addition, it uses inherent two-dimensional characteristics of image data and offers user-friendly instruction to assembler programmer The proposed two-dimensional addressing mode is applicable to DSP, media processor, graphic device, and so on. In this paper, we propose a new concept of two-dimensional addressing mode and an efficient hardware implementation method of it.

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Design and Implementation of a Data Mining Query Processor (데이터 마이닝 질의 처리를 위한 질의 처리기 설계 및 구현)

  • Kim, Chung-Seok;Kim, Kyung-Chang
    • The KIPS Transactions:PartD
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    • v.8D no.2
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    • pp.117-124
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    • 2001
  • A data mining system includes various data mining functions such as aggregation, association and classification, among others. To express these data mining function, a powerful data mining query language is needed. In addition, a graphic user interface(GUI) based on the data mining query language is needed for users. In addition, processing a data mining query targeted for a data warehouse, which is the appropriate data repository for decision making, is needed. In this paper, we first build a GUI to enable users to easily define data mining queries. We then propose a data mining query processing framework that can be used to process a data mining query targeted for a data warehouse. We also implement a schema generate a data warehouse schema that is needed to build a data warehouse. Lastly, we show the implementation details of a query processor that can process queries that discover association rules.

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Design of a Parallel Rendering Processor Architecture with Effective Memory System (효과적인 메모리 구조를 갖는 병렬 렌더링 프로세서 설계)

  • Park Woo-Chan;Yoon Duk-Ki;Kim Kyoung-Su
    • The KIPS Transactions:PartA
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    • v.13A no.4 s.101
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    • pp.305-316
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    • 2006
  • Current rendering processors are organized mainly to process a triangle as fast as possible and recently parallel 3D rendering processors, which can process multiple triangles in parallel with multiple rasterizers, begin to appear. For high performance in processing triangles, it is desirable for each rasterizer have its own local pixel cache. However, the consistency problem may occur in accessing the data at the same address simultaneously by more than one rasterizer. In this paper, we propose a parallel rendering processor architecture resolving such consistency problem effectively. Moreover, the proposed architecture reduces the latency due to a pixel cache miss significantly. For the above two goals, effective memory organizations including a new pixel cache architecture are presented. The experimental results show that the proposed architecture achieves almost linear speedup at best case even in sixteen rasterizers.

OpenGL ES Compiler Implementation for Embedded Graphic Processor (임베디드 그래픽 프로세서를 위한 OpenGL ES 컴파일러 개발)

  • Im, Soo-Jun;Song, Jun-Sup;Shin, Dong-Kun
    • Proceedings of the Korean Information Science Society Conference
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    • 2012.06a
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    • pp.167-169
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    • 2012
  • 오늘날 휴대용 기기에서의 그래픽 처리 요구사항이 증가함에 따라 저전력, 저비용 그래픽 프로세서의 필요성이 대두되고 있다. 이에 따라 크로노스 그룹은 휴대기기를 위한 그래픽 API 표준인 OpenGL ES 2.0을 발표하였다. 본 논문에서는 OpenGL ES 2.0을 상정하여 구성된 그래픽 프로세서를 위한 쉐이더 컴파일러를 개발하고 최적화하는 연구를 수행하였다. 개발된 컴파일러는 OpenGL ESSL로 작성된 쉐이더 프로그램을 정상적으로 컴파일하고 동작시켰으며 타겟 GPU에 적합한 최적화 기법을 적용하여 쉐이더 프로그램의 크기를 최대 10%가량 절감하고 성능을 10~15%가량 향상시켰다.

A Design of a Verification System for a 3D Graphic Geometry Engine (3D 그래픽 가속기를 위한 검증시스템의 설계 및 구현)

  • Song, In-Seok;Ha, Jin-Seok;Kim, Myung-Hwan;Lee, Kwang-Yeob;Jo, Tae-Hyun
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.663-666
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    • 2005
  • The geometry stage, which performs the transformation and lighting operations of vertices, became the critical part in 3D graphics pipeline. In this paper, we have planned and designed the Geometry Processor for the better and more efficient way to process the real-time 3D using the floating point unit. We also designed a verification system for Geometry engine. It is implemented with Xilinx-Virtex2 and Visual C++.NET. In the Synopsis, we confirmed 100 MHz performance and 137107 cell area of Geometry Engine.

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Development of a Post-Processing Program for Flow Analysis Based on the Object-Oriented Programming Concept (OOP 개념에 기초한 유동해석용 후처리 프로그램 개발)

  • Myong, Hyon-Kook;Ahn, Jong-Ki
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.32 no.1
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    • pp.62-69
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    • 2008
  • A post-processing program based on the OOP(Object-Oriented Programming) concept has been developed for flow visualization of the flow analysis code(PowerCFD) using unstructured cell-centered method. User-friendly GUI(GTaphic User Interface) has been built on the base of MFC(Microsoft Foundation Class). The program is organized as modules by classes including those based on VTK(Visualization ToolKit)-library, and these classes are made to function through inheritance and cooperation which is an important and valuable OOP concept. The major functions of this post-processor program are introduced and demonstrated, which include mesh plot, contour plot, vector plot, surface plots, cut plot, clip plot, xy-plot and streamline plot as well as view manipulation (translation, rotation, scaling etc).

A Virtual Instrumentation System Based on Three-Dimensional Current Coordinates for Monitoring Power Quality (전력품질 모니터링을 위한 3차원 전류 좌표계 기반의 가상 계측 시스템)

  • 정영국;임영철;김영철
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.52 no.3
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    • pp.124-132
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    • 2003
  • The goal of this paper is to propose a virtual instrumentation system based on three dimensional current coordinates for monitoring power quality A developed system with various experimental graphic screens and numerical results is made up 586-PC and DSP(digital signal processor) board, power quality analyzing and evaluating software for windows. Power parameters are analyzed using correlation signal processing techniques based on the correlation between voltage and current waveforms. Analysis. results are visualized by 3-D current coordinates, and it Is compared and evaluated with conventional time / frequency domain. To verify the validity of the proposed system, power and harmonic parameters of single phase induction motor drives is analyzed and verified.

A Study on Robot Simulator by use of Personal Computer Graphics (개인용 컴퓨터 그래픽스를 사용한 로보트 시뮬레이터의 연구)

  • Jun, Hyang-Sig;Choi, Young-Kiu
    • Proceedings of the KIEE Conference
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    • 1992.07a
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    • pp.351-353
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    • 1992
  • Recently, robot plays an important role in factory automation and its use is rapidly increasing. In paticular, modern industry tends to need the robot to adjust itself swiftly to new workcell. But, robot is to be taught of operator through teaching box in order that it can carry out new tasks. In the process, interruption of the production line is frequent and so much time and expense are required. Computer Graphic Simulator(CGS) provides a useful tool to overcome such a problem. In this paper, CGS consists of teaching mode and execution mode. The 5-axis Rhino robot is modelled in IBM-PC/386 compatible 32-bit personal computer with 80387 co-processor and the simulator performs defined operations on the computer screen.

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