• 반도체디스플레이기술학회지
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• 제9권2호
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• pp.97-102
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• 2010

Propagation modes of symmetric metal-insulator-metal SPP waveguides are analyzed. Main characteristics of these waveguides such as mode effective index, propagation length, and penetration depths are calculated at the telecom wavelength for different layer thickness. We adopt Au, Al as a metal material and air, glass as a dielectric material and obtain different optical characteristics. The surface plasmon characteristics in this paper provide a numerical insight for designing nanostructure metal plasmon waveguide.

• 한국산학기술학회논문지
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• 제6권6호
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• pp.497-501
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• 2005

Dry film 공정에 의해 PDP(Plasma Display Panel)용 무연 투명유전체를 제조하였다. 여러 슬러리 조성으로부터 고밀도 green sheet를 제조하는데 최적의 조성을 선정하였다. 한편, 슬러리는 양질의 green sheet를 제작하는데 적합한 shear thinning 특성을 나타냈다. 제조한 투명유전체의 열팽창계수는 유리기판인 PD-200과 유사한 $97{\times}10^{-7}/^{\circ}C$로 측정되었다. PD-200에 접합된 투명유전체의 단면 주사현미경 관찰로부터 두 층은 갭이 없이 매우 견실히 접합되어 있음을 확인할 수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.311-311
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• 2013

The resistance switching memory devices have several advantages to take breakthrough for the limitation of operation speed, retention, and device scale. Especially, the metal-oxide materials such as ZnO are able to fabricate on the flexible and visible transparent plastic substrate. Also, the quantum dots (QDs) embedded in dielectric layer could be improve the ratio between the low and the high resistance becauseof their Coulomb blockade, carrier trap and induced filament path formation. In this study, we irradiated 0.2-MeV-electron beam on the ZnO/QDs/ZnO structure to control the defect and oxygen vacancy of ZnO layer. The metal-oxide QDs embedded in ZnO layer on Pt/glass substrate were fabricated for a memory device and evaluated electrical properties after 0.2-MeV-electron beam irradiations. To formation bottom electrode, the Pt layer (200 nm) was deposited on the glass substrate by direct current sputter. The ZnO layer (100 nm) was deposited by ultra-high vacuum radio frequency sputter at base pressure $1{\times}10^{-10}$ Torr. And then, the metal-oxide QDs on the ZnO layer were created by thermal annealing. Finally, the ZnO layer (100 nm) also was deposited by ultra-high vacuum sputter. Before the formation top electrode, 0.2 MeV liner accelerated electron beams with flux of $1{\times}10^{13}$ and $10^{14}$ electrons/$cm^2$ were irradiated. We will discuss the electrical properties and the physical relationships among the irradiation condition, the dislocation density and mechanism of resistive switching in the hybrid memory device.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2001년도 춘계학술대회 논문집
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• pp.1121-1124
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• 2001

In this study, we verify th effects of pattern density on interlayer dielectric chemical mechanical polishing process based on the analysis of Preston's equation and confirm this analysis by several experiments. Appropriate modeling equation, transformed form Preston's equations used in glass polishing, will be suggested and described the effects of this modeling during pattern wafer ILD CMP. Results indicate that the modeling is well agreed to middle density structure of the die in pattern wafer, but has some error in low and high density structure of the die. Actually, the die used in Fab, was designed to have a appropriate density, therefore this modeling will be suitable for estimating the results of ILD CMP.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.526-529
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• 2002

Various fluoride films on a glass substrate were prepared and characterized in order to determine the best seed layer for a microcrystalline silicon (${\mu}c$-Si) film growth. Among the various group-IIA-fluoride systems, the $CaF_2$films on glass substrates illustrated (220) preferential orientation and a lattice mismatch of less than 0.7% with Si. $CaF_2$ films exhibited a dielectric constant between $4.1{\sim}5.2$ and an interface trap density ($D_{it}$ as low as $1.8{\times}10^{11}\;cm^{-2}eV^1$. Using the $CaF_2$/glass structure, we were able to achieve an improved ${\mu}c$-Si film at a process temperature of 300 $^{\circ}C$. We have achieved the ${\mu}c$-Si films with a crystalline volume fraction of 65%, a grain size of 700 ${\AA}$, and an activation energy of 0.49 eV.

• 한국세라믹학회지
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• 제46권2호
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• pp.146-154
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• 2009

It is necessary to minimize the thickness of Ni inner electrode layer and to improve the coverage of inner electrode, for the purpose of developing the ultra high-capacity multi layered ceramic capacitor (MLCC). Thus, low temperature sintering of dielectric $BaTiO_3$ ceramic should be precedently investigated. In this work, the relationship between dielectric properties of MLCC and batch condition such as mixing and milling methods was investigated in the $BaTiO_3$(BT)-Dy-Mg-Ba system with borosilicate glass as a sintering agent. In addition, several chip properties of MLCC manufactured by low temperature sintering were compared with conventionally manufactured MLCC. It was found that low temperature sintered MLCC showed better DC-bias property and lower aging rate. It was also confirmed that the thickness of Ni inner electrode layer became thinner and the coverage of inner electrode was improved through low temperature sintering.

• 전력전자학회논문지
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• 제21권2호
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• pp.111-116
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• 2016

This paper proposes a high-frequency (MHz) LLC resonant converter for a capacitor coupling wireless power transfer (CCWPT). The CCWPT uses electric field in the coupling capacitor between the transmitter and receiver electrodes with a dielectric layer. Given that capacitance is very small and the impedance is large, transferring power with a simple series resonance is difficult. Therefore, the high frequency (MHz) and high Q factor LLC converter is proposed to reduce the impedance of the coupling capacitance and to obtain a high output voltage. This paper deals with the operation analysis of the proposed LLC converter and a theoretical capacitance estimation. The operation and features of the proposed CCWPT LLC converter is verified with a 4.2 W prototype for charging mobile devices.

• 대한기계학회논문집A
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• 제34권2호
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• pp.245-253
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• 2010

전자기기부품에 적용되는 회로기판의 패키지 공정상에서 가해지는 온도변화에 따른 신뢰성 평가시 발생되는 문제들은, 주로 회로기판을 구성하고 있는 기본 재료들의 열팽창 계수 차이 및 시간의존성 물성에 의해 영향을 받는다. 특히, 인쇄회로기판 내부 회로층 사이에서 절연 역할을 수행하는 유리섬유강화 복합재료와 같은 수지몰딩 고분자 재료는 온도에 따른 물성변화 뿐만 아니라, 변형 및 하중이 가해지는 시간에 대한 물성변화도 고려해야 하는 점탄성 성질을 나타낸다. 본 논문에서는 인쇄회로기판에 사용되는 주요 고분자 재료인 유리섬유강화 복합재의 시간 및 온도에 따른 점탄성 특성을 규명하기 위하여, 단축인장 모드의 응력완화 시험과 크리프 시험을 각각 수행하였다. 또한, 고분자 재료 점탄성 물성의 영향성을 파악하기 위하여, 유한요소해석을 이용한 인쇄회로기판의 예비가열 공정 상에서 가해지는 온도변화에 따른 열변형을 평가하였다. 이러한 해석결과를 바탕으로, 인쇄회로기판과 같이 고분자재료를 사용하는 전자회로 구조물의 수치해석 기반의 열변형 예측시 점탄성 물성의 고려 필요성을 검증하였다.

• 한국재료학회지
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• 제12권6호
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• pp.458-463
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• 2002

Carbon nanotubes were synthesized at various conditions using Ni-catalytic thermal chemical vapor deposition method and their characteristic properties were investigated by SEM, TEM and Raman spectroscopy. Carbon nanotubes were formed on very fine Ni-catalytic particles. The carbon nanotubes synthesized by thermal decomposition of acetylene at $700^{\circ}C$ had a coiled shape, while those synthesized at $850^{\circ}C$ showed a curved and Y-shape having a bamboo-like morphology. It was found that the carbon nanotube was also made on the fine Ni-catalytic particles formed on the surface of 100~400nm sized large ones after pretreatment with $NH_3$.ber composites show the high dielectric constant and large conduction loss which is increased with anisotropy of fiber arrangement. It is, therefore, proposed that the glass and carbon fiber composites can be used as the impedance transformer (surface layer) and microwave reflector, respectively. By inserting the foam core or honeycomb core (which can be treated as an air layer) between glass and carbon fiber composites, microwave absorption above 10 dB (90% absorbance) in 4-12 GHz can be obtained. The proposed fiber composites laminates with sandwitch structure have high potential as lightweight and high strength microwave absorbers.

• 한국진공학회지
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• 제15권3호
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• pp.266-272
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• 2006

외부전극 형광램프의 구동에서 과도한 전력을 인가하면, 외부전극 부분의 유리관 표면에 작은 원형의 구멍(핀홀)이 발생하여 램프가 파손된다. 핀홀은 외부전극과 유리관을 유전층으로 하는 캐패시터의 절연파괴이며, 이러한 절연파괴력은 인가되는 전력에 비례한다. 유전상수가 K인 램프에 흐르는 전류가 작을 때, 핀홀이 발생하는 유리관의 절연파괴 전기장의 세기는 약 3K kV/mm,이다. 이러한 절연파괴 전기장의 세기는 램프에 흐르는 전류가 커질수록 작아진다.