• Journal of the Korean Society of Manufacturing Process Engineers
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• v.10 no.2
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• pp.9-15
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• 2011

In order to develop a practical postprocessor for 5-axis machining, the general equations of numerically controlled (NC) data for 5-axis configurations with not only non-orthogonal rotary axes but also orthogonal rotary axes were exactly expressed by the inverse kinematics, and a Windows-based postprocessor written in Visual Basic was developed according to the proposed algorithm. The developed postprocessor is a general system that suitable for all kinds of 5-axis machine tool with orthogonal and non-orthogonal rotary axes. Through implementation of the developed postprocessor and verification by a cutting simulation and machining experiment, the effectiveness of the proposed algorithm is confirmed. Compatibility is improved by allowing exchange of data formats such as rotational tool center position (RTCP) controlled NC data, vector post NC data, and program object file (POF) cutter location (CL)data, and convenience is increased by adding the function of work-piece origin offset. Consequently, the technology of practical post-processor for 5-axis machining is developed.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1465-1469
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• 2003

In general satellite verification process, the AOCS (Attitude & Orbit Control Subsystem) should be verified through several kinds of verification test which can be divided into two major category like FBT (Fixed Bed Test) and polarity test. And each test performed in different levels such as ETB (Electrical Test Bed) and satellite level. The test method of FBT is to simulate satellite dynamics with sensors and actuators supported by necessary environmental models in ETB level. The VDS (Vehicle Dynamic Simulator) try to make the real situation as possible as the on-board processor will undergo after launch. The purpose of FBT test is to verify that attitude control logic function and hardware interface is designed as expected with closed loop simulation. The VDS is one of major equipments for performing FBT and consists of software and hardware parts. The VDS operates in VME environments with target board, several commercial boards and custom boards based on the VxWorks real time operating system. In order to make time synchronization between VDS and satellite on-board processor, high reliable semaphore was implemented to make synchronization with the interrupt signal from on-board processor. In this paper, the real-time operating environment used on VDS equipment is introduced, and the hardware and software configurations of VDS summarized in the systematic point of view. Also, we try to figure out the operational concept of VDS and AOCS verification test method with close-loop simulation.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1141-1144
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• 2005

일반 컴퓨터에서 중앙처리장치와 메모리 사이의 병목 현상인 "Von Neumann Bottleneck"을 보이는데 본 논문에서는 이러한 문제점을 해소하고 검색위주의 응용분야에서 우수한 성능을 보이는 확장 가능한 범용 Associative Processor(AP) 구조를 제안하였다. 본 연구에서는 Associative computing을 효율적으로 수행할 수 있는 명령어 세트를 제안하였으며 다양하고 대용량 응용분야에도 적용할 수 있도록 구조를 확장 가능하게 설계함으로써 유연한 구조를 갖는다. 12 가지의 명령어가 정의되었으며 프로그램이 효율적으로 수행될 수 있도록 명령어 셋을 구성하고 연속된 명령어를 하나의 명령어로 구현함으로써 처리시간을 단축하였다. 제안된 프로세서는 bit-serial, word-parallel로 동작하며 대용량 병렬 SIMD 구조를 갖는 32 비트 범용 병렬 프로세서로 동작한다. 포괄적인 검증을 위하여 명령어 단위의 검증 뿐 아니라 최대/최소 검색, 이상/이하 검색, 병렬 덧셈 등의 기본적인 병렬 알고리즘을 검증하였으며 알고리즘은 처리 데이터의 개수와는 무관한 상수의 복잡도 O(k)를 갖으며 데이터의 비트 수만큼의 이터레이션을 갖는다.

• The Journal of the Acoustical Society of Korea
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• v.20 no.7
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• pp.94-100
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• 2001

When using a sample covariance matrix data in paucity of snapshots, adaptive matched field processing will have problem in inverting covariance matrix due to the rank deficiency. The general solutions are diagonal loading and eigenanalysis methods, but there is a significant bias in the power output. This paper presents a quantitative study of bias of power output and the performance of source localization through the simulation and the measured data analysis in fixed source case using the diagonal loading method for the minimum variance processor. Results show that the bias in power output is reduced and the performance of source localization is improved when the number of snapshots is greater than the number of array sensors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.74-79
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• 2007

In general, the high cost, long time, and complex steps are required in the design and implementation of MPSoC(Multi-Processor System on a Chip), therefore a platform is used to test the functionality and performance of IPs(Intellectual Properties). In this paper, we study a platform architecture to verify IPs based on Interconnect Network among processors, and show that the MPSoC platform gives better performance than a single processor for an application program.

• Journal of Biomedical Engineering Research
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• v.16 no.4
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• pp.403-414
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• 1995

It is very difficult to quantize the ECG analysis because the decision criterion for ECG is different with each other depending on the medical specialists of the heart and there are measured detecting errors for each ECG measurement system. Therefore, we developed the real-time ECG identification system using digital fuzzy processor for STD-BUS, in order to reduce ambiguity generated in the process of ECG identification and to analyze the irregular ECG stastically to ECG's repetition interval. The variables such as AGE (months), width of QRS, average RRI, and RRI were used to classify the ECG, and were applied to ECG signal indentification system which is developed for the purpose of research. It was found that the automatic diagnosis of ECG signal was possible in the real time process which was impossible in general process of algorithm.

• 전자공학회논문지 IE
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• v.48 no.3
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• pp.20-25
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• 2011

We developed a method of accelerating the operation speed of communication systems for SDR(Software Defined Radio) systems in WiBro environment. In this paper, we propose a new scheme of using GPU(Graphics Processing Unit) for implementing the communication system which perform with the functionality of SDR. In general, communication systems is made by DSP(Digital Signalling Processor) or FPGA(Field Programmable Gate Array). However, in this case, there are exist the problem of implementation and debugging caused by each CPU characteristic. The GPU is optimized for vector processing because it usually consists of multiple processors and each processor in GPU is composed of a set of threads. We also developed Framework to use GPU and CPU resources effectively for reducing the operation time. From the various simulation, it is confirmed that GPU system have good performance in WiBro system.

• Proceedings of the KOSOMBE Conference
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• v.1997 no.05
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• pp.342-344
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• 1997

Owing to technical advances in very large-scale integrated circuits (VLSI), high-speed digital signal processing (DSP) chips become fast enough to allow for real-time implementation of hearing aid algorithms in units small enough to be wearable. In this paper, we present a digital hearing aid processor (DHAP) chip built around a general-purpose 16-bit DSP core. The designed DHAP performs a nonlinear loudness correction of 8 octave frequency bands based on audiometric measurements. By employing a programmable DSP, the DHAP provides all the flexibility needed to implement audiological algorithms. In addition, the has a low power feature and $5.410\times5.720mm^2$ dimensions that fit for wearable devices.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.50-52
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• 2005

Research interests in PQ(Power Quality) measurement and monitoring system have been increased. This paper describes an experimental result for monitoring system that monitors power quality and undesirable accidents when distributed generations are connected to the power grid. Prior to develop a physical monitoring system for distributed generation applications, we constitute a mesuring system for the general PQ factors. In this paper, an approach to how to measure the PQ elements is presented by using TMS320C6701 processor. Simulation results using the PSCAD and the power system simulation equipment Dobel have verified the proposed measurement system.

• International Journal of Advanced Culture Technology
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• v.4 no.4
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• pp.23-29
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• 2016

In this paper, the learning technique for CNN processor on vehicle is proposed. In the case of conventional CNN processors, weighted values learned through training are stored for use, but when there is distortion in the image due to the weather conditions, the accuracy is decreased. Therefore, the method of enhancing the input image for classification is general, but it has the weakness of increasing the processor size. To solve this problem, the CNN performance was improved in this paper through the learning method of the distorted image. As a result, the proposed method showed improvement of approximately 38% better accuracy than the conventional method.