• The Journal of Korean Institute of Communications and Information Sciences
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• v.37C no.11
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• pp.1162-1169
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• 2012

One of the important operational requirements for mission critical Ethernet networked system is having the fault tolerant capability. Such capability can be obtained by equipping multiport Network Interface Card (NIC) in each node in the system. Conventional NIC uses two or more Media Access Controls (MACs) and a co-processor for the MAC switching whenever an active port fails. Since firmware is needed for the co-processor, longer fail-over switching and degraded throughput can be generally expected. Furthermore the system upgrading requiring the firmware revision in each tactical node demands high cost. In this paper we propose a novel single MAC based NIC that does not use a co-processor, but just use general discrete building blocks such as MAC chip and switching chip, which results in better performances than conventional method. Experimental results validate our scheme.

• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.12
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• pp.3345-3356
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• 1994

A general purpose program, TURBO-3D, for the analysis of 3-D fluid flow in complex geometry has been developed, which employs a standard $k-\varepsilon$ turbulence model and a general nonorthogonal grid system. For the purpose of verification of the program and testing the applicability, turbulent flows in an S-shaped diffuser and turbulent flows over an backward facing step are solved and compared with the earlier results. Comparison with the results by the STAR-CD program has been also made for the same flow configuration and grid structure. The agreements are excellent and hence the program has been verified. Since the present program is applicable only on limited flow phenomena and lacks the pre-and post processor, further improvements toward these directions are being made.

• IT SoC Magazine
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• s.5
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• pp.30-34
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• 2005

전체 반도체 시장이 연평균 10.7% 성장할 것으로 예측되고 있는 중, DRAM과 Flash가 메모리반도체 시장을 주도적으로 끌어나갈 것으로 예상되며 SoC 분야에서는 Digital Signal Processor (DSP), General Purpose Logic, Standard Linear가 시장을 주도적으로 이끌어 나갈 것으로 점쳐진다. 특히 General Purpose Logic은 SoC 전체에서 가장 높은 13.6%의 성장을 기록하면서 전체 반도체 시장에서 차지하는 비중도 5.9%에서 6.9%로 1% 상승하여 빠른 성장을 보이면서 시장 내의 비중이 제고될 것으로 예상된다

• The Transactions of the Korean Institute of Electrical Engineers
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• v.32 no.9
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• pp.305-314
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• 1983

This paper presents a general purpose data acquisition system based on the microprocessor system with M 6800. instrument and lograrithmic amplifiers and A/D converters are used to implement a signal conditioner for a various kinds of signals. The proposed system has a function such that the processor may select the one of the input signals as will and also it is proved that the system may control the control signal and digital converted signal through I/O port of PIA. Practical measurement by the proposed system shows in good results.

• Proceedings of the Korea Society for Simulation Conference
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• 1994.10a
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• pp.32-32
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• 1994

In this example, a message passing based multicomputer system with general interdonnedtion network is considered. After multicomputer systems are developed with morm-hole routing network, topologies of interconecting network are not major considertion for process management and resource sharing. Tehre is an independeent operating system kernel oneach node. It communicates with other kernels using message passingmechanism. Based on this architecture, the problem is how mech does performance degradation will occur in the case of processor sharing on multicomputer systems. Processor sharing between application programs is veryimprotant decision on system performance. In almost cases, application programs running on massively parallel computer systems are not so much user-interactive. Thus, the main performance index is system throughput. Each application program has various communication patterns. and the sharing of processors causes serious performance degradation in hte worst case such that one processor is shared by two processes and another processes are waiting the messages from those processes. As a result, considering this problem is improtant since it gives the reason whether the system allows processor sharingor not. Input data has many parameters in this simulation . It contains the number of threads per task , communication patterns between threads, data generation and also defects in random inupt data. Many parallel aplication programs has its specific communication patterns, and there are computation and communication phases. Therefore, this phase informatin cannot be obtained random input data. If we get trace data from some real applications. we can simulate the problem more realistic . On the other hand, simualtion results will be waseteful unless sufficient trace data with varisous communication patterns is gathered. In this project , random input data are used for simulation . Only controllable data are the number of threads of each task and mapping strategy. First, each task runs independently. After that , each task shres one and more processors with other tasks. As more processors are shared , there will be performance degradation . Form this degradation rate , we can know the overhead of processor sharing . Process scheduling policy can affects the results of simulation . For process scheduling, priority queue and FIFO queue are implemented to support round-robin scheduling and priority scheduling.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.05a
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• pp.600-602
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• 2021

With the development of the mobile industry and growing interest in artificial intelligence (AI) technology, a lot of research for AI processors which applicable to embedded systems is under study. When implementing AI to embedded systems, the design should be considered the restriction of resource and power consumption. Moreover, it is efficient to include a dedicated hardware accelerator in order to complement the low computational performance of the embedded system. In this paper, we propose an stand-alone embedded AI processor. The proposed AI processor includes a hardware accelerator that is dedicated to the distance-based AI algorithm and a general-purpose MCU that supports flexible programmability for application to various embedded systems. The AI processor was designed with Verilog HDL and verified by implementing on Field Programmable Gate Array (FPGA).

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.722-724
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• 1988

In this study, 8 ch. FECG signal storage system with general cassette recorder and amplifier is developed, and simulated LMS algorithm. In future we construct real time FECG monitor system that is used digital signal processor.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.4
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• pp.227-235
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• 2011

This paper describes a PMSM control algorithm for realizing a low-cost motor drive system using a general purpose microcontroller. The proposed sensorless algorithm consists of the current observer and the sensorless scheme based on instantaneous reactive power. Also the control board system is not the high-cost DSP(digital signal processor) system but the general purpose microcontroller and it allows to reduce the unit cost of the motor system. However the clock frequency of the proposed microcontroller is one-fifths for the clock frequency of the DSP. In addition, the switching frequency must be selected as the lower frequency because of complex mathematic modeling of the sensorless algorithm. the low switching frequency augments the noise of the motor and might make accurate speed control impossible. Thus this paper proposes the optimization method to supplement the drawback of the general purpose microcontroller and the usefulness of the proposed method is verified through the experiment.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.11
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• pp.527-539
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• 2008

This paper presents a performance estimation technique based on queuing analysis for on-chip bus matrix architectures of Multi-Processor System-on-Chips(MPSoCs). Previous works relying on time-consuming simulation are not able to explore the vast design space to cope with increasing time-to-market pressure. The proposed technique gives accurate estimation results while achieving faster estimation time than cycle -accurate simulation by order of magnitude. We consider the followings for the modeling of practical memory subsystem: (1) the service time with the general distribution instead of the exponential distribution and (2) multiple-outstanding transactions to achieve high performance. The experimental results show that the proposed analysis technique has the accuracy of 94% on average and much shorter runtime ($10^5$ times faster at least) compared to simulation for the various examples: the synthetic traces and real-time application, 4-channel DVR.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.10
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• pp.6673-6678
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• 2015

Recently, the free form buildings are constructed frequently. Exterior and interior components of these buildings have the free cross-section and a curved shape. So, There are many usages of classical finite element having tapered section and free-style shape. Some general commercial applications like ETABS, SAP2000, MIDAS are usually used for the safety evaluation of the free form structures. However, there are some limits in the accuracy of structural analysis and the length of analysis time because a very complicated finite element mesh have to be used. Therefore, In this study, a pre and post program module was developed to take advantage of general 3-D curved beam element which has a free-style curved shape and mathematical backgrounds. Pre-post processing module has been developed in this study was developed to control the curvature of the curved members by the NURBS control points. As a result, fast geometric modeling than was possible commercial applications. In addition, realistic depiction of the shape and behavior patterns were possible because of the free-form building allows visual check of the free form.