• Transactions of the Korean Society of Machine Tool Engineers
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• v.15 no.3
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• pp.53-58
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• 2006

This study deals with the method of post-processing in the automatic tool path generation for 5-axis NC machining. The 5-axis NC machining cannot only cope with the manufacturing of complicated shapes, but also offers numerous advantages such as reasonable tool employment, great reduction of set-up process and so on. Thus 5-axis NC machining has been used for aircraft parts, mold and die as well as for complicated shapes such as impeller, propeller and rotor. However, most of the present CAM systems for 5-axis NC machining have limited functions in terms of tool collision, machine limits and post-processing. Especially 5-axis machine configurations are various according to the method which the rotational axes are adapted with the table and spindle. For that reason, In many cases the optimal numerical control (NC) data cannot be obtained or considerable time is consumed. To solve this problem, we applied a general post-processor for 5-axis NC machining. The validity of this post-processor should be experimentally confirmed by successfully milling to a helix shaped workpiece.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.2
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• pp.251-256
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• 2017

Recently, multicore processor system is widely adopted not only in general purpose computers but also in embedded systems and mobile devices in order to improve performance. Since the power dissipation issue of multicore processor system is very significant, it must be estimated accurately in the early design stage. In this paper, a fast power analysis tool for a high performance multicore processor based on the trace-driven simulator has been developed. To achieve it, the power dissipation of each hardware unit per core are added. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed to estimate the average power dissipation per instruction.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.370-374
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• 2005

This study deals with the method of post-processing in the automatic tool path generation for 5-axis NC machining. The 5-axis NC machining cannot only cope with the manufacturing of complicated shapes, but also offers numerous advantages such as reasonable tool employment, great reduction of set-up process and so on. Thus 5-axis NC machining has been used fur aircraft parts, mold and die as well as for complicated shapes such as impeller, propeller and rotor. However, most of the present CAM systems for 5-axis NC machining have limited functions in terms of tool collision, machine limits and post-processing. Especially 5-axis machine configurations are various according to the method which the rotational axes are adapted with the table and spindle. For that reason, in many cases the optimal numerical control (NC) data cannot be obtained or considerable time is consumed. To solve this problem, we applied a general post-processor fur 5-axis NC machining. The validity of this post-processor should be experimentally confirmed by successfully milling to a helix shaped workpiece.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.515-518
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• 1998

This paper describes a direct transfer method of multimedia data stream between multimedia processor and network device without using system memory. The hardware architecture and functions for direct transfer, the method to transfer multimedia data to and from the multimedia processor and etc are described. Comparing the proposed method with general methods, I show that the direct transfer method can decrease number of bus accesses and bus cycles.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.931-934
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• 1999

For applications in multimedia to which genuine RISC microprocessors are not suitably applicable, a new generation of fast and flexible microprocessors is required. In this paper, as a technique of integrating DSP functionality in a general RISC processor, a RISC that can execute DSP extension instructions is developed to improve the performance of multimedia application execution. This processor can execute DSP instructions in parallel with the execution of ALU instructions for efficient and fast execution. In addition, the execution ability of integer instructions is improved by enhancing the RISC core itself.

• Journal of Korea Society of Digital Industry and Information Management
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• v.14 no.4
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• pp.87-92
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• 2018

One of the problems with the base station equipment is that there is a large difference between the replacement time of the hardware equipment such as the base station equipment and the radio access equipment, and the evolution period of the communication standard. Therefore, the base station communication platform must be flexible enough to handle the evolving communication standards after purchase. Recent research on reconfigurable communications platforms has focused on the efficient architecture of the communications platform to meet these requirements through software downloads while still using existing hardware. This paper presents a prototype of a base station communications platform based on the ETSI standard reconfigurable architecture. The communication platform presented in this paper is implemented as an ETSI standard reconfigurable architecture using a general-purpose DSP (Digital Signal Processor). In the implemented prototype, we verify the real-time feasibility of communication protocol updates through software reconfiguration.

• KIISE Transactions on Computing Practices
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• v.23 no.2
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• pp.97-103
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• 2017

Many hardware-based regular expression matching architectures have been proposed for high-performance matching. In particular, regular expression processors, which perform pattern matching by treating the regular expressions as the instruction sequence like general purpose processors, have been proposed. After instruction sequence and data are provided in the instruction memory and data memory, respectively, a regular expression processor can perform pattern matching. To use a regular expression processor as a coprocessor, we need the host interface to transfer the instruction and data into the memory of a regular expression processor. In this paper, we design and implement the host interface between a host and a regular expression processor in the DE1-SoC board and the application program interface. We verify the operations of the host interface and a regular expression processor by executing the application programs which perform pattern matching using the application program interface.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.4
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• pp.135-141
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• 2020

Today, CPUs in general-purpose computers such as servers, desktops and laptops, as well as home appliances and embedded systems, consist mostly of multicore processors. In order to improve performance, it is required to use an out-of-order execution processor by Tomasulo algorithm as each core processor. An out-of-order execution processor with Tomasulo algorithm can execute the available instructions in any order and perform speculation in order to reduce control dependencies. Therefore, the performance of an out-of-order execution processor can be significantly improved compared to an in-order execution processor. In this paper, an out-of-order execution processor using Tomasulo algorithm and ARM instruction set is designed using VHDL record data types and simulated by GHDL. As a result, it is possible to successfully perform operations on programs written in ARM instructions.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.10
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• pp.573-581
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• 2002

In this paper, we propose a mediaprocessor of dual-cache architecture which is composed of the multimedia data cache and the general-purpose data cache to prevent performance degradation caused by memory delay. In the proposed processor architecture, multimedia data that are written in subword instructions are loaded in the multimedia data cache and the remaining data are loaded in the general-purpose data cache. Also, Ive use multi-block prefetching scheme that fetches two consecutive data blocks into a cache at a time to exploit the locality of multimedia data. Experimental results on MPEG and JPEG benchmark programs show that the proposed processor architecture results in better performance than the processor equipped with single data cache.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.541-556
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• 2005

The memory access latency of the system has been a primary factor of performance degradation in single-processor system and multi-processor system. The remote memory access latency takes a lot of overhead over the local memory access latency especially in the distributed shared-memory system. To resolve this problem, the multi-level cache architecture that contains a remote cache in the multi-processor system has been proposed. In this paper, we propose a new cache replacement policy that improves the performance of the multi-processor system with the remote cache. If the multi-level cache keeps the multi-level inclusion(MLI) property and uses the LRU(Least Recently Used) cache replacement policy, the LRU information of the higher-level cache(a processor cache) would be different with that of the lower-level cache(a remote cache). In this situation, the replacement of a remote cache line can induce the exchange of a processor cache line that is used by the processor. It is a main factor of performance degradation in a whole system. To alleviate this disadvantage of the LRU replacement polity, the new policy analyses tht processor's remote memory access pattern of each node and uses this information to reduce the number of invalidations of the useful cache line in the higher-level cache. The new replacement policy of the remote cache can improve the performance by $3.5\%$ in maximum and $2.5\%$ in average on SPLASH-2 benchmarks, compared to the general LRU cache replacement policy.