• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.1-9
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• 1992

Radio data system is a next-generation broadcasting system of digital information communication which multiplexes the digital data into the FM stereo signal in VHF/FM band and provides important and convenient service features. And radio data are composed of groups which are divided into 4 blocks with information word and check word. In this paper, radio data receiver is developed which recovers and process radio data to provide services. Then we confirm that 7dB SNR is required to be 10S0-5TBER of demodulation. Deconding process of shortened-cyclic-decoder has been simulated by computer. Also, the time-compression (by 16 times) method has been adopted for the RDS features post-processing. Via the error probability calculation, simulation and experimentation, the developed receiver system is proved to satisfy the system specification of EBU and implemented by general logic gates and analog circuits.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.205-216
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• 1996

In this paper we propose an efficient robust path delay fault test genration algorithm for detection of path delay faluts in combinational ligic circuits. In the proposed robust test genration approach, the testability measure is computed for all gates in the circuit under test and these computed values are used to genrate weighted random delay test vetors for detection of path delay faults. For genrated robust test vectors, we perform fault simulation on ISCAS '85 benchmark circuits using parallel pattern technqieus. The results indicate that the proposed test genration method not only increases the number of detected robust path delay faults but also reduces the time taen to genrate robust tests.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.20-28
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• 1997

In this paper, quantization and inverse quantizatio unit, a sa component of MPEG-2 moving picture compression system, ar edesigned. In the processing of quantization, this design adopted newly designed arithmetic units in which quantization matrices and scale code was expressed with SD(signed-digit) code. In the arithmetic unit of inverse quantization, quantization scale code, which has 5-bits length, is splited into two pieces; 2-bits for control code, 3-bits for quantization data, and the method to devise quantization step size is proposed. The design was coded with VHDL and synthesis results in that it consumed about 6,110 gates, and operating speed is 52MHz.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2003.05a
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• pp.402-408
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• 2003

Now many major airports in the world which operate strategic alliance or Hub & Spoke system have met capacity restriction and confusion problems. And the time and the walking distance for boarding to flight are important standard to measure customer convenience. And the effective gate assignment guarantees customers convenience as well as increasing airport capacity without expanding established airport equipments. So it can be a major concern to manage airports. So this paper formulate gate assignment problem in the hub airport not quadratic assignment problem but a improved single-period integer problem which is minimize local and transit passengers I walking distance. As a result, this study will present a method producing optimal gate assignment result using optimization software. We use real flights and gates data in the national airport, so we will compare a assignment results with a real airport assignment results and previous researches and analyze those results.

• Proceedings of the Korea Concrete Institute Conference
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• 2003.05a
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• pp.1035-1040
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• 2003

This research investigates the actual data and construction technology of the massive bottom slab placed by $23,000m^3$ concrete quantity in site of the in-ground type LNG receiving terminal having 20,000kl storage capacity. The purpose of this study is to determine the optimum mix design and control the actual concreting procedures including concrete production, transportation, placement, vibrating and curing in site. For this purpose, the optimum mix design using ternary blended cement(furnace slag cement＋fly ash) and under piping method having 11 gates and 7 distributors are selected. As test results of actual construction, concrete placement is finished during 68hours with good success and obtained the good quality of the fresh and hardened concrete including slump, air contents, no-segregation, compressive strength and low hydration heat. Also, actual data for all of concrete procedures are proved successful and satisfied with our specifications.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.701-707
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• 1987

This paper is concerned with an accurate delay time modling of the ED MOS logic gates and its application to the multiple delay logic simulator. The proposed delay model of the ED MOS logic gate takes account of the effects of not only the loading conditions but also the slope of the input waveform. Defining delay as the time spent by the current imbalance of the active inverter to charge and discharge the output load, with respect to physical reference levels, rise and fall model delay times are obtained in an explicit formulation, using optimally weighted imbalance currents at the end points of the voltage transition. A logic simulator which uses multiple rise/fall delays based on the model as decribed in the above has been developed. The new delay model and timing verification method are evaluated with repect to delay accuracy and execution time.

• Proceeding of EDISON Challenge
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• 2015.03a
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• pp.343-346
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• 2015

Ultra-thin body transistor is one of the emerging devices since it control leakage current flows through substrate. In addition, it can be operated by double gates, thus, its on/off current ratio is higher than conventional counterpart. In this paper, we design and investigate a CMOS inverter based on ultra-thin body MOSFETs to estimate its performance in real application. NEGF (non-equilibrium Green's function) method is used to obatain relationship between drain current and voltage. DC transfer is extracted from the relationship, and FO4 (fanout-of-4) propagation delay is reported as 5.1 ps estimated by a simple model.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.433-434
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• 2007

This paper describes a low-voltage dynamic random-access memory (DRAM) focusing on subthreshold leakage reduction during self-refresh (sleep) mode. By sharing a power switch, multiple iterative circuits such as row and column decoders have a significantly reduced subthreshold leakage current. To reduce the leakage current of complex logic gates, dual channel length scheme and input vector control method are used. Because all node voltages during the standby mode are deterministic, zigzag super-cutoff CMOS is used, allowing to Preserve internal data. MTCMOS technique Is also used in the circuits having no need to preserve internal data. Sub-1.2-V 1-Gb mobile DDR DRAM employing all these low-power techniques was designed in a 60 nm CMOS technology and achieved over 77% reduction of overall leakage current during the self-refresh mode.

• Journal of Information Display
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• v.6 no.4
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• pp.11-15
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• 2005

We propose a current mode logic circuit design method for LTPS TFT for enhancing circuit operating speed. Current mode inverter/buffers with passive resistive load had been designed and fabricated. Measurement results indicated that the smaller logic swing of the current mode allowed significantly faster operation than the static CMOS. In order to reduce the chip size, both all pTFT and all nTFT active load current mode inverter/buffer had been designed and analyzed by HSPICE simulation. Even though the active load current mode circuits were inferior to the passive load circuits, it was superior to static CMOS gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.3B
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• pp.584-591
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• 2000

In distributed arithmetic-based architecture for an inner product between two length-N vectors, the size of the ROM increases exponentially with N. Moreover, the ROMs are generally the bottleneck of speed, especially when their size is large. In this paper, a ROM size reduction technique for DA( distributed arithmetic ) is proposed. The proposed method is based on modified OBC( offset binary coding) and control circuit reduction technique. by simulations, it is shown that the use of the proposed technique can result in reduction in the number of gates up to 50%.