• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.70-70
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• 2009

In this paper, we proposed 2500V Non punch-through(NPT) Insulated gate bipolar transistor(IGBT) for high voltage industry application. we carried out optimal simulation for high efficiency of 2500V NPT IGBT according to size of device. In results, we obtaind design parameter with 375um n-drift thickness, 15um gate length, and 8um emitter windows. After we simulate with optimal parameter, we obtained 2840V breakdown voltage and 3.4V Vce,sat. These design and process parameter will be used designing of more 2000V NPT IGBT devices.

• Journal of the Korean Institute of Rural Architecture
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• v.21 no.4
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• pp.53-60
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• 2019

The purpose of this study is to investigate the change of Hidden gates form with the times. Fortresses position is constructed on the Korea mountain ranges. Hidden gate, one of facilities to construct fortress among various factors, represents as route of supplies way, ask for rescue, or counterattack plan to come in. The shape of hidden gate changes depend on land form, function, and time period. Previous research partially based on archeology or history. This research analyze Namhan mountain Namhansansung, one of the highest hidden gates count in Korea, distributive by main fortress, Bong-am fortress, Hanbong fortress. Nahhan Mountain fortress repeatedly affected by King Injo in Joseon Dynasty. As a result, Nahhan Mountain fortress consist of hidden gates alternation depend on the time of establishment or extension which makes different shape or size.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1008-1011
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• 2005

In this study, the field emission display with carbon nanotube emitter is developed for the large size HDTV application. Two structures for electron beam focusing are developed on the typical top-gate cathode. The metal grid and focusing gate structure are proved to be effective for the focusing. The data switching voltage for the double gate structure is lower than 30V which is competitive value in respect of the cost for driver electronics. The brightness and color gamut are comparable to those of the commercial product such as CRT.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2594-2596
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• 1999

Recently, white good market has interest with inverter product, which has merit to on/off type with respect to energy saving and noise. But, inverter product's cost is rising, because of adding inverter circuit component. To reduce cost, inverter gate drive trend is using HVIC which needs only single voltage. Also using HVIC, designer can compact PCB'size. This paper shows application technique and key point of designing HVIC

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.4
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• pp.273-279
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• 2010

In this paper, we proposed 2500 V Non punch-through(NPT) Insulated gate bipolar transistor(IGBT) for high voltage industry application. we carried out optimal simulation for high efficiency of 2500 V NPT IGBT according to size of device. In results, we obtaind design parameter with 375 um n-drift thickness, 15 um gate length, and 8um emitter windows. After we simulate with optimal parameter, we obtained 2840 V breakdown voltage and 3.4V Vce,sat. These design and process parameter will be used designing of more 2000 V NPT IGBT devices.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.859-862
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• 2003

This paper proposes an emulation environment for SoC designs using small number of large gate-count FPGA's and a PC system. To overcome the pin limitation problem in partitioning the design when the design size overwhelms the FPGA gate count, we use bus splitter modules that replicate on-chip bus signals in one FPGA to arbitrary number of other FPGA's with minimal pin count. The proposed scheme is applied to the emulation of 2 million gate multimedia processing chip using two Xilinx Viretex-2 6000 FPGA devices in 6.6MHz operating frequency. An ARM core, memories, camera and LCD display are modeled in software using dual 2GHz Pentium-III processors. This scheme can be utilized for more than 2 FPGA's in the same ways as two FPGA case without losing emulation speed.

• Design & Manufacturing
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• v.13 no.4
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• pp.34-39
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• 2019

In this paper, in order to improve the formability and quality of the injection molded parts in the molds for molding the motorcycle rear cowl injection molded parts with different volumes at the same time, the flow of the molded parts is changed through the injection molding CAE analysis by changing the gate position, runner size and position. It is to find the optimum gate position, the diameter of the runner and the position where the balance is equal. The molded article formed by the optimization resulted in the uniformity of the molten resin at the same time at the corner of the product, thereby maintaining the flow balance favorable for mass production at lower injection pressure.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.21 no.6
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• pp.998-1002
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• 2012

This paper investigates the behavior of bubbles trapped in the in-mold coating (IMC) process. Silicon oil with different viscosity, 100, 150, 200, 300 and 400cps, was selected instead of the coating materials. To observe the flow front inside, a special mold was designed, where front plate was made of transparent material (acrylate). The overall size of front plate was $150mm{\times}120mm$. Mold gate location can be changed from up to down. Four heaters were used to investigate the effectiveness of temperature. The results show that silicon viscosity, mold gate location and mold temperature play an important role on the appearance of bubbles trapped in IMC process.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.403-404
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• 2012

We fabricated TFT devices with the GeSe channel. A single device consists of a Pt source and drain, a Ti glue layer and a GeSe chalcogenide channel layer on SiO2/Si substrate which worked as the gate. We confirmed the drain current with variations of gate bias and channel size. The I-V curves of the switching device are shown in Fig. 1. The channel of the device always contains amorphous state, but can be programmed into two states with different threshold voltages (Vth). In each state, the device shows a normal Ovonic switching behavior. Below Vth (OFF state), the current is low, but once the biasing voltage is greater than Vth (ON state), the current increases dramatically and the ON-OFF ratio is high. Based on the experiments, we draw the conclusion that the gate voltage can enhance the drain current, and the electric field by the drain voltage affects the amorphous-amorphous transition. The switching device always contains the amorphous state and never exhibits the Ohmic behavior of the crystalline state.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.280-281
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• 2011

We fabricated the devices of TFT type with the amorphous chalcogenide channel. A single device consists of a Pt source and drain, a Ti glue layer and a GeSe chalcogenide channel layer on SiO2/Si substrate which worked as the gate. We confirmed the drain current with variations of gate bias and channel size. The I-V curves of the switching device are shown in Fig. 1. The channel of the device always contains amorphous state, but can be programmed into two states with different threshold voltages (Vth). In each state, the device shows a normal Ovonic switching behavior. Below Vth (OFF state), the current is low, but once the biasing voltage is greater than Vth (ON state), the current increases dramatically and the ON-OFF ratio is about 4 order. Based on the experiments, we contained the conclusion that the gate voltage can enhance the drain current, and the electric field by the drain voltage affects the amorphous-amorphous transition. The switching device always contains the amorphous state and never exhibits the Ohmic behavior of the crystalline state.