• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.767-773
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• 2017

In this paper, we propose a design of Intra prediction angular mode decision for HEVC encoder. Intra prediction coding of HEVC is a method for predicting a current block by referring to samples reconstructed around a current block. Intra prediction supports a total of 35 modes with 1 DC mode, 1 Planar mode, and 33 Angular modes. Intra prediction coding of HEVC works by performing all 35 modes for efficient encoding. However, in order to process all of the 35 modes, the computational complexity and operational time required are high. Therefore, this paper proposes comparing the difference in the value of the original pixel, using an algorithm that determines angular mode efficiently. This new algorithm reduces the Hardware size. The hardware which is proposed was designed using Verilog HDL and was implemented in 65nm technology. Its gate count is 14.9K and operating speed is 2GHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.50-56
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• 2016

This paper proposes the architecture and design of intra prediction circuit for a multi-decoder supporting UHD images. The proposed circuit supports not only the latest video compression standard HEVC but also H.264. In addition to the basic function of performing intra prediction, this circuit has the capability of performing the reference sample filter operation defined in the H.264 standard, and the smoothing and strong sample filter operations defined in the HEVC standard. We reduced the circuit size by sharing the circuit blocks for common operations and internal storage, and improved the circuit performance by parallel processing. The proposed circuit was described at RTL using Verilog HDL and its functionality was verified by using NC-Verilog of Cadence. The RTL circuit was synthesized by using Design Compiler of Synopsys and 130nm standard cell library. The synthesized gate-level circuit consists of 69,694 gates and processes 100 ~ 280 frames per second for 4K-UHD HEVC images at the maximum operation frequency of 157MHz.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.13-22
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• 1998

In this paper, we propose a high-performance BICS(built-in current sensor) which is fabricated in 0.8${\mu}{\textrm}{m}$ single-poly two-metal process for IDDQ testing of CMOS VLSI circuit. The CUT(circuit under test) is 4-bit full adder with a bridging fault. Using two nMOSs that have different size, two bridging faults that have different resistance values are injected in the CUT. And controlling a gate node, we experimented various fault effects. The proposed BICS detects the faulty current at the end of the clock period, therefore it can test a CUT that has a much longer critical propagation delay time and larger area than conventional BICSs. As expected in the HSPICE simulation, experimental results of fabricated chip demonstrated that the proposed BICS can exactly detect bridging faults in the circuit.

• Journal of IKEEE
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• v.19 no.3
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• pp.392-399
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• 2015

This paper proposes a unified $4{\times}4$ transform architecture for HEVC and VP9 codec to reduce hardware size. It performs HEVC $4{\times}4$ IDCT, HEVC $4{\times}4$ IDST, VP9 $4{\times}4$ IDCT, and VP9 $4{\times}4$ IADST in a unified hardware. HEVC $4{\times}4$ IDCT and VP9 $4{\times}4$ IDCT have same IDCT computation except for the scales of coefficients. Similarly, HEVC $4{\times}4$ IDST and VP9 $4{\times}4$ IADST have same IDST computation except for the scales of coefficients. Furthermore, IDCT and IDST have quite a lot of similarity, so they can share some hardwares in common. So the proposed hardware performs all 4 operations in a unified hardware, where each operation has its own multiplication coefficients with shared butterfly adders. The synthesized block in 0.18 um technology is 6,679 gates, and the gate count is reduced by 25.3% in comparison with conventional designs.

• Journal of IKEEE
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• v.19 no.3
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• pp.378-384
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• 2015

In conventional HEVC inverse core transform architectures, extra $n{\times}n$ inverse transform block is added to $2n{\times}2n$ inverse transform block, and it operates as one $2n{\times}2n$ inverse transform block or two $n{\times}n$ inverse transform blocks. Thus, same number of pixels are processed in the same time, but it suffers from increased hardware size due to extra $n{\times}n$ inverse transform block. To avoid this problem, a novel $8{\times}8$ HEVC inverse core transform architecture was proposed to eliminate extra $4{\times}4$ inverse transform block based on multiplier reuse. This paper extends this approach and proposes a novel HEVC $16{\times}16$ inverse core transform architecture. Its frame processing time is same in $4{\times}4$, $8{\times}8$, and $16{\times}16$ inverse core transforms, and reduces gate counts by 13%.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.109-118
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• 1998

This paper presents an ASIC implementation of video encoder which converts either digital RGB or YCbCr to S-video(Y/C) and composite video signal. The video timing signal of this encoder includes horizontal sync., vertical sync. signal and blanking, and this encoder supports field identification signal which is convenient for video editing. The encoder has been designed in the 4 stages pipeline structure to assure the stable operation of each submodule. The proposed encoder requires only 20K gates ,which is a 40% reduction in hardware compared with [13]. The designed encoder was fabricated in $0.65{\mu}m$ SOG triple metal CMOS technology. Chip size is $3.7478mm {\times} 4.4678mm$ including PAD, gate counts is 19,468 and dissipated power is 0.9W.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.11
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• pp.34-43
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• 1999

A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.66-72
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• 2009

This paper proposes an efficient binary arithmetic encoder for CABAC which is used one of the entropy coding methods for H.264/AVC. The present binary arithmetic encoding algorithm requires huge complexity of operation and data dependency of each step, which is difficult to be operated in fast. Therefore, renormalization exploits 2-stage pipeline architecture for efficient process of operation, which reduces huge complexity of operation and data dependency. Context model updater is implemented by using a simple expression instead of transIdxMPS table and merging transIdxLPS and rangeTabLPS tables, which decreases hardware size. Arithmetic calculator consists of regular mode, bypass mode and termination mode for appearance probability of binary value. It can operate in maximum speed. The proposed binary arithmetic encoder has 7282 gate counts in 0.18um standard cell library. And input symbol per cycle is about 1.

• Journal of Korea Multimedia Society
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• v.7 no.1
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• pp.35-43
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• 2004

In this paper, we proposed a vehicle recognition and electronic toll collection system with detection and classification of vehicle identification mark and emblem as well as recognition of vehicle license plate to unman toll fee collection system or incoming/outcoming vehicles to an institution. In the proposed algorithm, we first process pre-processing step such as noise reduction and thinning from the rear side input image of vehicle and detect vehicle mark, emblem and license plate region using intensity variation informations, template masking and labeling operation. And then, we classify the detected vehicle features regions into vehicle mark and emblem as well as recognize characters and numbers of vehicle license plate using hybrid and seven segment pattern vector. To show the efficiency of the proposed algorithm, we tested it on real vehicle images of implemented vehicle recognition system in highway toll gate and found that the proposed method shows good feature detection/classification performance regardless of irregular environment conditions as well as noise, size, and location of vehicles. And also, the proposed algorithm may be utilized for catching criminal vehicles, unmanned toll collection system, and unmanned checking incoming/outcoming vehicles to an institution.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.571-578
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• 2012

In this paper, we propose two main points. The first is the constraint for logic synthesis, and the second is an efficient logic synthesis method. Logic synthesis is a process to obtain the gate-level netlist from RTL (register transfer level) codes using logic mapping and optimization with the specified constraints. The result of logic synthesis is tightly dependent on constraint and logic synthesis method. Since the size and timing can be dramatically changed by these, we should precisely consider them. In this paper, we present the considering items in the process of logic synthesis by using our experience and experimental results. The proposed techniques was applied to a circuit with the hardware resource of about 650K gates. The synthesis time for the hybrid method was reduced by 47% comparing the bottom-up method and It has better timing property about slack than top-down method.