• 제목/요약/키워드: Gate size

검색결과 531건 처리시간 0.026초

Development and Performance Investigation on a 60kW Induction Motor for EV Propulsion

  • Chun, Yon-Do;Park, Byoung-Gun;Kim, Dong-Jun;Choi, Jae-Hak;Han, Pil-Wan;Um, Sukkee
    • Journal of Electrical Engineering and Technology
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    • 제11권3호
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    • pp.639-643
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    • 2016
  • This paper introduces the development process and investigation of a 60kW induction motor for electric vehicles. We present performance improvement in the induction motor of electric vehicle using copper die-casting based on a multi-gate process. Copper die-casting motors can reduce the size of the motor, the loss of the rotor, and material costs. We also introduce electromagnetic, thermal, mechanical design and analysis results that satisfy the design and the performance requirements. In order to analyze losses accurately of induction motor, commercial finite element analysis is done considering PWM voltage and thermal characteristics by using lumped-circuit parameters. Experimental tests are also carried out to validate the traction motor design.

압전변압기를 이용한 LCD Backlight 구동 (LCD Backlight Drive Using The Piezoelectric Transformer)

  • 임성운;최연호;원철호;구본호;김이국
    • 조명전기설비학회논문지
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    • 제17권2호
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    • pp.28-33
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    • 2003
  • 기계적인 에너지를 전기적인 에너지로 변환시키는 장치인 압전변압기는 고전압\ulcorner고효율의 소형변압기이다. 압전변압기는 노트북용 LCD backlight 구동장치로 적합하며, 공진주파수에서 동작시 거의 정현파에 가까운 교류파형을 출력하는 장치이다. 본 논문에서는 입력 DC 전압으로부터 FET를 구동시키는 게이트 신호로 변환시킨 다음 LC공진을 통하여 정현파를 생성시켜 압전변압기를 구동시키는 인버터에 대하여 논의하였다. 실험결과 압전변압기의 전압 이득과 공진주파수는 부하에 비례하며, 전압 이득은 입력전압의 변화에는 무관하게 나타났다.

PWM 쵸퍼와 전류형 인버터를 이용한 계통연계형 태양광발전시스템 (A Utility Interactive Photovoltaic Generation System using PWM Chopper and Current Source Inverter)

  • 이승환;성낙규;오봉환;검성남;이훈구;김용주;한경희
    • 전력전자학회논문지
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    • 제3권4호
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    • pp.323-329
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    • 1998
  • 계통연계형 태양광발전시스템을 PWM 쵸퍼와 전류형 인버터로 구성하였다. 전류형 인버터의 직류리액터를 경감하는 방법으로, 직류측에 병렬공진회로를 삽입함에 따라 맥동전력의 일부를 교류 전해콘덴서에 축적하여 직류전류의 맥동을 억제하는 방법과, 쵸퍼의 변조파를 전원주파수의 2배로 제어하여 직류전류의 맥동을 억제하는 것을 비교 검토하였다. 그리고 태양전지전류와 쵸퍼의 변조율만을 이용하여 태양전지가 항상 최대출력점에서 동작하도록 하였다. 계통과 연계함으로서 출력전력이 부하전력보다 큰 경우에는 잉영전력을 계통전원에 공급하고, 발전전력 부하전력에 대해 부족한 경우에는 계통전원이 부족분을 공급하는 것을 확인하였다.

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Electrical Characteristics of Ge-Nanocrystals-Embeded MOS Structure

  • Choi, Sam-Jong;Park, Byoung-Jun;Kim, Hyun-Suk;Cho, Kyoung-Ah;Kim, Sang-Sig
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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    • pp.3-4
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    • 2005
  • Germanium nanocrystals(NCs) were formed in the silicon dioxide($SiO_2$) on Si layers by Ge implantation and rapid thermal annealing process. The density and mean size of Ge-NCs heated at $800^{\circ}C$ during 10 min were confirmed by High Resolution Transmission Electron Microscopy. Capacitance versus voltage(C-V) measurements of MOS capacitors with single $Al_2O_3$ capping layers were performed in order to study electrical properties. The C-V results exhibit large threshold voltage shift originated by charging effect in Ge-NCs, revealing the possibility that the structure is applicable to Nano Floating Gate Memory(NFGM) devices.

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미세접촉프린팅공정을 이용한 플렉시블 디스플레이 유기박막구동소자 제작 (Fabrication of Organic Thin Film Transistor(OTFT) for Flexible Display by using Microcontact Printing Process)

  • 김광영;조정대;김동수;이제훈;이응숙
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2006년도 춘계학술대회 논문집
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    • pp.595-596
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    • 2006
  • The flexible organic thin film transistor (OTFT) array to use as a switching device for an organic light emitting diode (OLED) was designed and fabricated in the microcontact printing and low-temperature processes. The gate, source, and drain electrode patterns of OTFT were fabricated by microcontact printing which is high-resolution lithography technology using polydimethylsiloxane(PDMS) stamp. The OTFT array with dielectric layer and organic active semiconductor layers formed at room temperature or at a temperature tower than $40^{\circ}C$. The microcontact printing process using SAM(self-assembled monolayer) and PDMS stamp made it possible to fabricate OTFT arrays with channel lengths down to even nano size, and reduced the procedure by 10 steps compared with photolithography. Since the process was done in low temperature, there was no pattern transformation and bending problem appeared. It was possible to increase close packing of molecules by SAM, to improve electric field mobility, to decrease contact resistance, and to reduce threshold voltage by using a big dielecric.

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현장 측정을 통한 관개용수로의 손실량 추정 (Estimation of Water Loss in Irrigation Canals through Field Measurement)

  • 이용직;김필식;김선주;지용근;주욱종
    • 한국농공학회논문집
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    • 제50권1호
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    • pp.13-21
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    • 2008
  • Water losses in irrigation canals are mainly estimated as the sum of conveyance and delivery water loss. The losses occur via the evaporation, infiltration, gate operation and water distribution processing. Recently, the study regarding these water losses are not satisfactory enough, also delivery water loss has not been mainly considered on field design. The objective of this study is to investigate and analyze the volume of water loss in irrigation canals considering condition of actual farm land. A field measurement was performed at four research sites, which are managed by Korea Rural Community & Agriculture Corporation, to evaluate conveyance and delivery water loss for 2 years. The measurement was performed by canal type, size and designed flow using the inflow-outflow method at a major points such as start and end of each canal, derivation point of canal and inlet of paddy fields. Results of this study showed that water loss ratio in lateral canals was bigger than that of main canal unlike current design standard and the loss decrease as flow increase. The total of water loss ratio including conveyance and delivery water loss in several irrigation canals ranged between 33.25 and 45.0%.

Characterization of Triode-type CNT-FED Fabricated using Photo-sensitive CNT Paste

  • Kwon, Sang-Jik;Chung, Hak-June;Lee, Sang-Heon;Choi, Hyung-Wook;Shin, Young-Hwa;Lee, Dal-Ho;Lee, Jong-Duk
    • Journal of Information Display
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    • 제5권4호
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    • pp.18-22
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    • 2004
  • A carbon nanotube field emission display (CNT FED) panel with a 2 inch diagonal size was fabricated through screen printing of a prepared photo-sensitive CNT paste and vacuum in-line sealing technology. After surface treatment of the patterned CNT, only the carbon nanotube tips are uniformly exposed on the surface. The diameter of the exposed CNTs are usually about 20nm. The sealing temperature of the panel is around 390 $^{\circ}C$ and the vacuum level is obtained with $1.4{\times}10^{-5}$torr at the sealing. The field emission properties of the diode type CNT FED panel are characterized. Currently, we are in the process of developing a triode type CNT FED with a self-aligned gate-emitter structure.

나노 CMOS 소자 적용을 위한 질소 분위기에서 형성된 질화막을 이용한 폴리실리콘 적층 구조 (A Stacked Polusilicon Structure by Nitridation in N2 Atmosphere for Nano-scale CMOSFETs)

  • 호원준;이희덕
    • 한국전기전자재료학회논문지
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    • 제18권11호
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    • pp.1001-1006
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    • 2005
  • A new fabrication method is proposed to form the stacked polysilicon gate by nitridation in $N_2$ atmosphere using conventional LP-CVD system. Two step stacked layers with an amorphous layer on top of a polycrystalline layer as well as three step stacked layers with polycrystalline films were fabricated using the proposed method. SIMS profile showed that the proposed method would successfully create the nitrogen-rich layers between the stacked polysilicon layers, thus resulting in effective retardation of dopant diffusion. It was observed that the dopants in stacked films were piled-up at the interface. TEM image also showed clear distinction of stacked layers, their plane grain size and grain mismatch at interface layers. Therefore, the number of stacked polysilicon layers with different crystalline structures, interface position and crystal phase can be easily controlled to improve the device performance and reliability without any negative effects in nano-scale CMOSFETs.

270 MHz Full HD H.264/AVC High Profile Encoder with Shared Multibank Memory-Based Fast Motion Estimation

  • Lee, Suk-Ho;Park, Seong-Mo;Park, Jong-Won
    • ETRI Journal
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    • 제31권6호
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    • pp.784-794
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    • 2009
  • We present a full HD (1080p) H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external memory access to fetch samples, which degrades the performance of the encoder. A novel approach to fast ME which uses shared multibank memory can solve these problems. The proposed pixel subsampling ME algorithm is suitable for fast motion vector searches for high-quality resolution images. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software, while sustaining the video quality without any conspicuous PSNR loss. The usage amount of shared multibank memory between the coarse ME and fine ME blocks is 93.6%, which saves external memory access cycles and speeds up ME. It is feasible to perform the algorithm at a 270 MHz clock speed for 30 frame/s real-time full HD encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.

EPI MOSFET의 문턱 전압 특성 분석 (Analysis for Threshold-voltage of EPI MOSFET)

  • 김재홍;고석웅;임규성;정학기;이종인
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2001년도 추계종합학술대회
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    • pp.665-668
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    • 2001
  • 최근 소자의 크기가 작아짐에 따라 집적도가 향상되었으며 크기 감소로 인한 전류-전압 특성의 열화 및 기생 커패시턴스에 의한 성능감쇠가 발생하였다. 이런 문제들을 해결하기 위해 여러 가지 구조들이 개발되고 있으며 본 논문에서는 고농도로 도핑된 ground plane 층위에 적층하여 만든 EPI 구조에 대해 조사 분석하였다. 이 구조의 특성과 임팩트 이온화 및 전계 그리고 I-V 특성 곡선을 저농도로 도핑된 LDD(Lightly Doped Drain) 구조와 비교 분석하였다. 소자의 채널 길이는 0.l0$\mu\textrm{m}$부터 0.06$\mu\textrm{m}$까지 0.01$\mu\textrm{m}$씩 스케일링하여 시뮬레이션 하였다.

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