• Title/Summary/Keyword: Gate size

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Relation of Conduction Path and Subthreshold Swing for Doping Profile of Asymmetric Double Gate MOSFET (비대칭 DGMOSFET의 도핑분포함수에 따른 전도중심과 문턱전압이하 스윙의 관계)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.8
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    • pp.1925-1930
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    • 2014
  • This paper has analyzed the relation of conduction path and subthreshold swing for doping profile in channel of asymmetric double gate(DG) MOSFET. Since the channel size of asymmetric DGMOSFET is greatly small and number of impurity is few, the high doping channel is analyzed. The analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. The conduction path and subthreshold swing are derived from this analytical potential distribution, and those are investigated for variables of doping profile, projected range and standard projected deviation, according to the change of channel length and thickness. As a result, subthreshold swing is reduced when conduction path is approaching to top gate, and that is increased with a decrease of channel length and a increase of channel thickness due to short channel effects.

The Change in the Buddhist Architecture of the Unified Silla Period (668-935) (통일신라시대(統一新羅時代) 불교건축(佛敎建築)의 변화(變化))

  • Kim, Sung-Woo
    • Journal of architectural history
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    • v.1 no.2 s.2
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    • pp.68-84
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    • 1992
  • The development of Buddhist architectures of the Unified Silla period have been generally understood to have paired pagoda instead of one which had been popular until before the unification. Besides the stylistic categorization of paired pagoda system, there had been no further investigation reported concerning whether there was any detailed process of change within the development of paired pagoda style. This paper aims to identify such change inside the development of paired pagoda style, which, externally, seems to be the same pattern of site design maintained throughout the period of Unified Silla that lasted for about three centuries. Since the temple sites of study are in the same pattern of layout, the method of investigation has to be such that can identify the subtle changes that, in external appearance, are not easily discernible. Hence, this research compared the dimensions of important measurement of five temple sites to be able to clarify the process of minor changes. Among many sites of Silla temples, only five were suitable for the research since detailed measurement were possible through field research or the report of excavation. They are the sites of Sachonwang-sa, Mangduk-sa, site of Kunsuri, and Bulguk-sa. Although the five sites have the same style of paired pagoda, it is clear that there were consistant flow of change. Even though the motivation of such change were not strong enough to change the site pattern itself, it resulted continuous minor changes such as the size and location of architectures. The size of image hall, for example, was growing larger and larger as time goes on, while, the size of Pagoda was getting smaller. In the same way, the size of middle gate became smaller while the size of lecture hall became larger, although the rate of change in these cases were not as severe as that of image hall and pagoda. At the same time, pagoda was coming closer to the middle gate leaving larger space in front of the image hall. Such aspect is even more meaningful considering the fact that the pagoda, from the 8th century in Japan and China, moved outside of the major precinct. The image hall, too, moved toward the middle gate slightly so that the space in front of the lecture hall became more spacious. Such changes, of course, were not accidental but they are the same continuous motivation of change that caused the changes before the period of unification. Enlargement of image hall and reduction of pagoda, for example, represent the changing relative importance of religious meaning. Hence, it is evident that one can not easily imterprete the development of one style only by categorizing it to be one same style. In the veiwpoint of the underlying motivation of change, the fact that one style persisted for a certain period of time, does not mean there had been no change, but means that it was the time of motivational accumulation, causing minor changes within the same style, to be able to create major change coming after.

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Design of Efficient FFT Processor for MIMO-OFDM Based SDR Systems (MIMO-OFDM 기반 SDR 시스템을 위한 효율적인 FFT 프로세서 설계)

  • Yang, Gi-Jung;Jung, Yun-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.12
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    • pp.87-95
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    • 2009
  • In this paper, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed scalable FFT processor can support the variable length of 64, 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate4eve1 circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 59% and 39%, respectively, compared with those of the 4-channel radix-2 single-path delay feedback (R2SDF) FFT processor. Also, compared with 4-channel radix-2 MDC (R2MDC) FFT processor, it is confirmed that the gate count and memory size are reduced by 16.4% and 26.8, respectively.

A Process Decomposition Strategy for Qualitative Fault Diagnosis of Large-scale Processes (대형공정의 정성적 이상진단을 위한 공정분할전략)

  • Lee Gibaek
    • Journal of the Korean Institute of Gas
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    • v.4 no.4 s.12
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    • pp.42-49
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    • 2000
  • Due to their size and complexity, it is very difficult to make diagnostic system for the whole chemical processes. Therefore, a systematic approach is required to decompose larpge-scale process into sub-processes and then diagnose them. This paper suggests a method for the minimization of knowledge base and flexible diagnosis to be used in qualitative fault diagnosis based on Fault-Effect Tree model. The system can be decomposed for flexible diagnosis, size reduction of knowledge base, and consistent construction of complex knowledge base. The new node, gate-variable, is introduced to connect the cause-effect relationships of each sub-process. For on-line diagnosis, off-line analysis is performed to construct Fault-Effect Trees of gate-variables as well as activation conditions of gate-variables. On-line diagnosis strategy is modified to get the same diagnosis result without system decomposition. The proposed method is illustrated with a fault diagnosis system for a large-scale boiler plant.

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The Effects of Nanocrystalline Silicon Thin Film Thickness on Top Gate Nanocrystalline Silicon Thin Film Transistor Fabricated at 180℃

  • Kang, Dong-Won;Park, Joong-Hyun;Han, Sang-Myeon;Han, Min-Koo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.2
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    • pp.111-114
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    • 2008
  • We studied the influence of nanocrystalline silicon (nc-Si) thin film thickness on top gate nc-Si thin film transistor (TFT) fabricated at $180^{\circ}C$. The nc-Si thickness affects the characteristics of nc-Si TFT due to the nc-Si growth similar to a columnar. As the thickness of nc-Si increases from 40 nm to 200 nm, the grain size was increased from 20 nm to 40 nm. Having a large grain size, the thick nc-Si TFT surpasses the thin nc-Si TFT in terms of electrical characteristics such as field effect mobility. The channel resistance was decreased due to growth of the grain. We obtained the experimental results that the field effect mobility of the fabricated devices of which nc-Si thickness is 60, 90 and 130 nm are 26, 77 and $119\;cm^2/Vsec$, respectively. The leakage current, however, is increased from $7.2{\times}10^{-10}$ to $1.9{\times}10^{-8}\;A$ at $V_{GS}=-4.4\;V$ when the nc-Si thickness increases. It is originated from the decrease of the channel resistance.

Analysis of optimum grid determination of water quality model with 3-D hydrodynamic model using environmental fluid dynamics code (EFDC)

  • Yin, Zhenhao;Seo, Dongil
    • Environmental Engineering Research
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    • v.21 no.2
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    • pp.171-179
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    • 2016
  • This study analyzes guidelines to select optimum number of grids to represent behavior of a given water system appropriately. The EFDC model was chosen as a 3-D hydrodynamic and water quality model and salt was chosen as a surrogate variable of pollutant. The model is applied to an artificial canal that receives salt water from coastal area and fresh water from a river from respective gate according to previously developed gate operation rule. Grids are subdivided in vertical and horizontal (longitudinal) directions, respectively until no significant changes are found in salinity concentrations. The optimum grid size was determined by comparing errors in average salt concentrations between a test grid systems against the most complicated grid system. MSE (mean squared error) and MAE (mean absolute error) are used to compare errors. The CFL (Courant-Friedrichs-Lewy) number was used to determine the optimum number of grid systems for the study site though it can be used when explicit numerical method is applied only. This study suggests errors seem acceptable when both MSE and MAE are less than unity approximately.

A Study of The Electrical Characteristics of Small Fabricated LTEIGBTs for The Smart Power ICs (스마트 파워 IC에의 활용을 위한 소형 LTEIGBT의 제작과 전기적인 특성에 관한 연구)

  • 오대석;김대원;김대종;염민수;강이구;성만영
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.338-341
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    • 2002
  • A new small size Lateral Trench Electrode Insulated Gate Bipolar Transistor (LTEIGBT) is proposed and fabricated to improve the characteristics of device. The entire electrode of LTEIGBT is placed to trench type electrode. The LTEIGBT is designed so that the width of device is 19$\mu\textrm{m}$. The latch-up current density of the proposed LTEIGBT is improved by 10 and 2 times with those of the conventional LIGET and LTIGBT The forward blocking voltage of the LTEIGBT is 130V. At the same size, those of conventional LIGBT and LTIGBT are 60V and 100V, respectively. Because that the electrodes of the proposed device is formed of trench type, the electric field in the device are crowded to trench oxide. We fabricated He proposed LTEIGBT after the device and process simulation was finished. When the gate voltage is applied 12V, the forward conduction currents of the proposed LTEIGBT and the conventional LIGBT are 80mA and 70mA, respectively, at the same breakdown voltage of 150V,

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A design of Encoder Hardware Chip For H.264 (H.264 Encoder Hardware Chip설계)

  • Kim, Jong-Chul;Suh, Ki-Bum
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.10a
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    • pp.100-103
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    • 2008
  • In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800k gate counts using Charterd 0.18um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

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A Novel Lateral Trench Electrode IGBT for Suprior Electrical Characteristics (인텔리전트 파워 IC의 구현을 위한 횡형 트렌치 전극형 IGBT의 제작 및 그 전기적 특성에 관한 연구)

  • 강이구;오대석;김대원;김대종;성만영
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.15 no.9
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    • pp.758-763
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    • 2002
  • A new small size Lateral Trench Electrode Insulated Gate Bipolar Transistor (LTEIGBT) is proposed and fabricated to improve the characteristics of device. The entire electrode of LTEIGBT is placed to trench type electrode. The LTEIGBT is designed so that the width of device is 19w. The latch-up current density of the proposed LTEIGBT is improved by 10 and 2 times with those of the conventional LIGBT and LTIGBT. The forward blocking voltage of the LTEIGBT is 130V. At the same size, those of conventional LIGBT and TIGBT are 60V and 100V, respectively. Because the electrodes of the proposed device is formed of trench type, the electric field in the device are crowded to trench oxide. When the gate voltage is applied 12V, the forward conduction currents of the proposed LTEIGBT and the conventional LIGBT are 80mA and 70mA, respectively, at the same breakdown voltage of 150V.

A design of Encoder Hardware Chip For H.264 (H.264 Encoder Hardware Chip설계)

  • Suh, Ki-Bum
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.12
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    • pp.2647-2654
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    • 2009
  • In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking Filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800K gate counts using Charterd 0.18 um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.