• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.12
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• pp.3626-3631
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• 2009

This study has provided some of the first experimental results of NMOSFET hot-carrier degradation for the analog circuit application. After hot-carrier stress under the whole range of gate voltage, the degradation of NMOSFET characteristics is measured in saturation region. In addition to interface states, the evidences of hole and electron traps are found near drain depending on the biased gate voltage, which is believed to the cause for the variation of the transconductance($g_m$) and the output conductance($g_{ds}$). And it is found that hole trap is a dominant mechanism of device degradation in a low-gate voltage saturation region, The parameter degradation is sensitive to the channel length of devices. As the channel length is shortened, the influence of hole trap on the channel conductance is increased. Because the magnitude of $g_m$ and $g_{ds}$ are increased or decreased depending on analog operation conditions and analog device structures, careful transistor design including the level of the biased gate voltage and the channel length is therefore required for optimal voltage gain ($A_V=g_m/g_{ds}$) in analog circuit.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.59-67
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• 2016

With the enhancement of built-in communication capabilities in various meters and wearable devices, which implies Internet of things (IoT), the demand of small-area embedded processors has increased. In this paper, we introduce a small-area 32-bit pipelined processor, Juno, which is available in the field of IoT. Juno is an EISC (Extendable Instruction Set Computer) machine and has a 2/3-stage pipeline structure to reduce the data dependency of the pipeline. It has a simple pipeline controller which only controls the program counter (PC) and two pipeline registers. It offers $32{\times}32=64$ multiplication, 64/32=32 division, $32{\times}32+64=64$ MAC (multiply and accumulate) operations together with 32*32=64 Galois field multiplication operation for encryption processing in wireless communications. It provides selective inclusion of these algebraic logic blocks if necessary in order to reduce the area of the overall processor. In this case, the gate count of our integer core amounts to 12k~22k and has a performance of 0.57 DMIPS/MHz and 1.024 Coremark/MHz.

• Journal of Korean Society of Environmental Engineers
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• v.35 no.2
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• pp.101-108
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• 2013

Ara Canal is the first artificial canal in Korea that connects the Han River and the Yellow Sea. Due to mixture of waters with different salinity and water quality, complicated hydrodynamic and water quality distributions are expected to occur inside the canal. An integrated hydrodynamic and water quality modeling system was developed using the 3 dimensional hydrodynamic model, EFDC (Environmental Fluid Dynamics Code) and the water quality model WASP (Water Quality Analysis and Simulation Program). According to the modeling results, BOD, TN, TP and Chl-a concentrations inside the canal were lower at the West Gate side than the Han River side since influent concentrations of the West Gate side are significantly lower. Chemical stratification due to salinity difference were more evident at the West Gate side as vertical salinity difference were more pronounced in this area. On the other hand, Chl-a concentrations showed more pronounced vertical distribution at the Han River side as Chl-a concentrations were higher in this area. It was notable that Dissolved Oxygen concentrations can be lower than 2 mg/L occasionally in the middle part of the canal. While major factor affecting DO concentrations in the canal are inflows via both gates, the other important factor was found to be BOD decay in the canal due to extended hydraulic residence time. This study can be used to predict hydrodynamic conditions and water quality in the canal during the year and thus can be helpful in the development of gate operation method of the canal.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1163-1170
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT which was specified as a standard for lightweight cryptography ISO/IEC 29192-2 is described. The PRESENT crypto-processor supports two key lengths of 80 and 128 bits, as well as four modes of operation including ECB, CBC, OFB, and CTR. The PRESENT crypto-processor has on-the-fly key scheduler with master key register, and it can process consecutive blocks of plaintext/ciphertext without reloading master key. In order to achieve a lightweight implementation, the key scheduler was optimized to share circuits for key lengths of 80 bits and 128 bits. The round block was designed with a data-path of 64 bits, so that one round transformation for encryption/decryption is processed in a clock cycle. The PRESENT crypto-processor was verified using Virtex5 FPGA device. The crypto-processor that was synthesized using a $0.18{\mu}m$ CMOS cell library has 8,100 gate equivalents(GE), and the estimated throughput is about 908 Mbps with a maximum operating clock frequency of 454 MHz.

• Journal of the Korean earth science society
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• v.21 no.5
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• pp.541-552
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• 2000

The variations of physical properties due to inflow of seawater by sluice gates operation were observed in Shihwa Lake. The distributions of salinity and temperature were investigated at 11 stations during February, 1997 to July, 1998. The salinity of water mass in Shihwa Lake before gate operation was ranged below 15psu and strong stratification due to inflow of seawater was observed at the depth of 11 m. In July 1997, temperature difference of 10^{\circ}C$ was occurred between the surface and bottom water due to strong solar radiation. During October 1997 to February 1998, inversion of temperature distribution, which the temperature of bottom water was higher than that of surface water, was observed. In July 1997, temperature, salinity, current speed and current direction were investigated by RCM-7 at St.3 for 56 days. When sea water was intruded in Shihwa Lake, the symmetric distribution of temperature and salinity was observed and it seems to be resulted from inflow of seawater with low temperature and high salinity. After January 1998, salinity of Shihwa Lake was increased over 30psu due to continuous gate operation and the stratification was weakened.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.61-68
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• 2008

In this paper, we propose an efficient hardware architecture and algorithm to increase an encoding process rate and implement a hardware for CABAC (Context Adaptive Binary Arithmetic Coding) which is used with one of the entropy coding ways for the latest video compression technique, H.264/AVC (Advanced Video Coding). CABAC typically provides a better high compression performance maximum 15% compared with CAVLC. However, the complexity of operation of CABAC is significantly higher than the CAVLC. Because of complicated data dependency during the encoding process, the complexity of operation is higher. Therefore, various architectures were proposed to reduce an amount of operation. However, they have still latency on account of complicated data dependency. The proposed architecture has two techniques to implement efficient pipeline architecture. The one is quick calculation of 7, 8th bits used to calculate a probability is the first step in Binary arithmetic coding. The other is one step reduced pipeline arcbitecture when the type of the encoded symbols is MPS. By adopting these two techniques, the required processing time was reduced about 27-29% compared with previous architectures. It is designed in a hardware description language and total logic gate count is 19K using 0.18um standard cell library.

• Korean Journal of Agricultural Science
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• v.17 no.2
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• pp.102-114
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• 1990

This study was carried out to analyze the operation of the sluice gates by taking Sabkyo Reservoir as the model, and to examine the formulae of the design criteria for the Agricultural Land Improvement Project by hydraulic model experiments. The results were summarized as follows ; 1. According to the records of gate operation for 9 years, the mean height of the opened gates was 4.13 m, the mean number of operated gates were 4.04, the average annual number of operation were 67 times, the average annual operating time were 192.5 hours, and the average operating time were 2.88 hours. 2. The water supplied through Sabkyo Reservoir was 88.15 megatons per year, which was about 1.4 times the effective storage capacity. And the annual volume of pumping in May, which is the most water demanding season, was 29.56 megatons in average. 3. As the submerged orifice was transformed into the surface orifice, the suggested formulae for the orifice flow on the design criteria for the Agricultural Land Improvement Project showed a discontinuous line on the transition zone. It should be improved, because it is different from the real hydraulic phenomena. 4. The formulae for the orifice flow which are divided into the submerged and surface orifices are being used. However, these formulae could be substituted for the formular, $q=C{\cdot}W\sqrt{2gH_1}$, if the discharge coefficient considering the reservoir water level, the sea water level, and the gate opening height is used.

• Journal of the Korea Society of Computer and Information
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• v.12 no.4
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• pp.249-256
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• 2007

AIn this paper, a new desist of LDI controller IC for general purpose is proposed for driving the LDI(LCD Driver Interface) controller in $4{\sim}9$ inches sized portable small-medium TFT-LCD(Thin Film Transistor addressed -Liquid Crystal Display) panel module. The designed LDI controller was verified on the FPGA(Reld Programmable Gate Array) test board, and was made the interactive operation with the commercial TFT-LCD panel successfully. The purpose of design is that it is standardized the LDI controller's operation by one LDI controller for driving all TFT-LCD panel without classifying the panel vendor, and size. The main advantage for new general-purpose LDI controller is the usage for the desist of all panel's SoG(System on a Glass) module because of the design for the standard operation. And in the previous method, it used each LDI controller for every LCD vendor, and panel size, but because a new one can drive all portable small-medium sized panel, it results in reduction of LDI controller supply price, and manufacturing cost of AV(Audio Video) board and panel. In the near future, the development of SoG IC(Integrated Circuit) for manufacturing more excellent functional TFT-LCD panel module is necessary. As a result of this research, the TFT-LCD panel can make more small size, and light weight, and it results in an upturn of domestic company's share in the world market. With the suggested theory in this paper, it expects to be made use of a basic data for developing and manufacturing for the SoG chip of TFT-LCD panel module.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.11
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• pp.2093-2099
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• 2016

This paper describes a design of crypto-processor that supports multiple block cipher algorithms of PRESENT, ARIA, and AES. The crypto-processor integrates three cores that are PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES), and AES-16b. The PRmo core implementing 64-bit block cipher PRESENT supports key length 80-bit and 128-bit, and four modes of operation including ECB, CBC, OFB, and CTR. The AR_AS core supporting key length 128-bit and 256-bit integrates two 128-bit block ciphers ARIA and AES into a single data-path by utilizing resource sharing technique. The AES-16b core supporting key length 128-bit implements AES with a reduced data-path of 16-bit for minimizing hardware. Each crypto-core contains its own on-the-fly key scheduler, and consecutive blocks of plaintext/ciphertext can be processed without reloading key. The crypto-processor was verified by FPGA implementation. The crypto-processor implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,500 gate equivalents (GEs), and it can operate with 55 MHz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1203-1212
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• 2013

In this paper, an intra prediction hardware architecture is proposed to reduce computational complexity of intra prediction in HEVC decoder. The architecture uses shared operation units and common operation units and adopts a fast smoothing decision algorithm and a fast algorithm to generate coefficients of a filter. The shared operation unit shares adders processing common equations to remove the computational redundancy. The unit computes an average value in DC mode for reducing the number of execution cycles in DC mode. In order to reduce operation units, the common operation unit uses one operation unit generating predicted pixels and filtered pixels in all prediction modes. In order to reduce processing time and operators, the decision algorithm uses only bit-comparators and the fast algorithm uses LUT instead of multiplication operators. The proposed architecture using four shared operation units and eight common operation units which can reduce execution cycles of intra prediction. The architecture is synthesized using TSMC 0.13um CMOS technology. The gate count and the maximum operating frequency are 40.5k and 164MHz, respectively. As the result of measuring the performance of the proposed architecture using the extracted data from HM 7.1, the execution cycle of the architecture is about 93.7% less than the previous design.