• Title/Summary/Keyword: Gate Operation

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High Temperature Characteristics of GaAs MESFETs for Maximum Transconductance (GaAs MESFET의 최대 트랜스컨덕턴스를 위한 고온특성)

  • 원창섭;김영태;한득영;안형근
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.14 no.4
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    • pp.274-280
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    • 2001
  • This paper presents transconductance (g$\_$m/( characteristics of GaAs MESFET's at high temperatures ranging from room temperature to 350$\^{C}$. GaAs MESFET of 0.3x750[㎛] gate dimension has been used to obtain the experimental data. Gate to source voltage(V$\_$GS/) has been controlled to obtain the temperature dependent characteristics for maximum transconductance g$\_$mmax/ of the device. Furthermore g$\_$mmax/ and expected g$\_$m/ have been traced with temperatures ranging from room temperature to 350$\^{C}$ also by compensating for C$\_$GS/ to maintain the optimum operation of the device. From the results, V$\_$GS/decreases as the operating temperature increases for optimum operation of the transconductance. Finally V$\_$GS/ has been optimized to trace g$\_$mmax/ and enhances the decreased g$\_$m/ with different temperatures.

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A High-Speed Matched Filter for Searching Synchronization in DSSS Receiver (DSSS 수신기에서 동기탐색을 위한 고속 정합필터)

  • 송명렬
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.10C
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    • pp.999-1007
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    • 2002
  • In this paper, the operation of matched filter for searching initial synchronization in direct sequence spread spectrum receiver is studied. The implementation model of the matched filter by HDL (Hardware Description Language) is proposed. The model has an architecture based on parallelism and pipeline for fast processing, which includes circular buffer, multiplier, adder, and code look-up table. The performance of the model is analyzed and compared with the implementation by a conventional digital signal processor. It is implemented on a FPGA (Field Programmable Gate Array) and its operation is validated in a timing simulation result.

A Performance-Oriented Intra-Prediction Hardware Design for H.264/AVC

  • Jin, Xianzhe;Ryoo, Kwangki
    • Journal of information and communication convergence engineering
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    • v.11 no.1
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    • pp.50-55
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    • 2013
  • In this paper, we propose a parallel intra-operation unit and a memory architecture for improving the performance of intra-prediction, which utilizes spatial correlation in an image to predict the blocks and contains 17 prediction modes in total. The design is targeted for portable devices applying H.264/AVC decoders. For boosting the performance of the proposed design, we adopt a parallel intra-operation unit that can achieve the prediction of 16 neighboring pixels at the same time. In the best case, it can achieve the computation of one luma $16{\times}16$ block within 16 cycles. For one luma $4{\times}4$ block, a mere one cycle is needed to finish the process of computation. Compared with the previous designs, the average cycle reduction rate is 78.01%, and the gate count is slightly reduced. The design is synthesized with the MagnaChip $0.18{mu}m$ library and can run at 125 MHz.

A New Basic Element for Neural Logic Functions and Capability in Circuit Applications

  • Omura, Yasuhisa
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.2 no.1
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    • pp.70-81
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    • 2002
  • This paper describes a new basic element which shows a synaptic operation for neural logic applications and shows function feasibility. A key device for the logic operation is the insulated-gate pn-junction device on SOI substrates. The basic element allows an interface quite compatible to that of conventional CMOS circuits and vMOS circuits.

Low voltage operating $InGaZnO_4$ thin film transistors using high-k $MgO_{0.3}BST_{0.7}$ gate dielectric (고유전 $MgO_{0.3}BST_{0.7}$ 게이트 절연막을 이용한 $InGaZnO_4$ 기반의 트랜지스터의 저전압 구동 특성 연구)

  • Kim, Dong-Hun;Cho, Nam-Gyu;Chang, Young-Eun;Kim, Ho-Gi;Kim, Il-Doo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.40-40
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    • 2008
  • $InGaZnO_4$ based thin film transistors (TFTs) are of interest for large area and low cost electronics. The TFTs have strong potential for application in flat panel displays and portable electronics due to their high field effect mobility, high on/off current ratios, and high optical transparency. The application of such room temperature processed transistors, however, is often limited by the operation voltage and long-tenn stability. Therefore, attaining an optimum thickness is necessary. We investigated the thickness dependence of a room temperature grown $MgO_{0.3}BST_{0.7}$ composite gate dielectric and an $InGaZnO_4$ (IGZO) active semiconductor on the electrical characteristics of thin film transistors fabricated on a polyethylene terephthalate (PET) substrate. The TFT characteristics were changed markedly with variation of the gate dielectric and semiconductor thickness. The optimum gate dielectric and active semiconductor thickness were 300 nm and 30 nm, respectively. The TFT showed low operating voltage of less than 4 V, field effect mobility of 21.34 cm2/$V{\cdot}s$, an on/off ratio of $8.27\times10^6$, threshold voltage of 2.2 V, and a subthreshold swing of 0.42 V/dec.

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Design of a MOSFET Monostable Multivibrator by Graphical Method (도식방법에 의한 MOSFET 단안정 멀티바이브레이터의 설계)

  • 심수보
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.13 no.1
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    • pp.11-15
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    • 1976
  • In a MOSFET multivibrator, the gate do not hold into a constant clamp voltage during a conduction period. The analysis of the operation and the 43sign of a MOSFET multivibrator circuit are much more discult than that using a bipolar transistor and a electron tube because of above reason. And therefore, in the designing procedures of the MOSFET monostable multivibrator of this paper, a graphical method is adopted in order to analyze and design easily. The voltage gain curves of the both FETs are drawn using a parameter the voltage Vc across the coupling condenser, and the curves are utilized to investigate the voltages of the drains and the gates and determine the gate bias voltage. The diagram gives also important informations for the design of the multivibrator.

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Threshold Voltage Movement for Channel Doping Concentration of Asymmetric Double Gate MOSFET (도핑농도에 따른 비대칭 이중게이트 MOSFET의 문턱전압이동현상)

  • Jung, Hakkee;Lee, jongin;Jeong, Dongsoo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2014.05a
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    • pp.748-751
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    • 2014
  • This paper has analyzed threshold voltage movement for channel doping concentration of asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET is generally fabricated with low doping channel and fully depleted under operation. Since impurity scattering is lessened, asymmetric DGMOSFET has the adventage that high speed operation is possible. The threshold voltage movement, one of short channel effects necessarily occurred in fine devices, is investigated for the change of channel doping concentration in asymmetric DGMOSFET. The analytical potential distribution of series form is derived from Possion's equation to obtain threshold voltage. The movement of threshold voltage is investigated for channel doping concentration with parameters of channel length, channel thickness, oxide thickness, and doping profiles. As a result, threshold voltage increases with increase of doping concentration, and that decreases with decrease of channel length. Threshold voltage increases with decrease of channel thickness and bottom gate voltage. Lastly threshold voltage increases with decrease of oxide thickness.

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The Variation of Water Quality due to Sulice Gate Operation in Shiwha Lake (시화호의 배수갑문 운용에 따른 수질변화)

  • 김종구;김준우;조은일
    • Journal of Environmental Science International
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    • v.11 no.12
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    • pp.1205-1215
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    • 2002
  • To evaluate the change for water quality after the water gate operation in Shiwha lake, in situ survey were conducted on september in 2000 and January, march, jane in 2001. Chemical characteristics and eutrophication level was estimated from the survey data. The water quality of the Shihwa lake was greatly affected by pollutant load from rainfall, and formation of stratification in summer and winter was increased to effect on nutrient release from sediment. Especially, high concentration of chlorophyll-a was occurred in autumn, due to increased nutrient, high water temperature and low salinity after rainfall runoff. The mean concentration of DIN, DIP were 0.346mg/L, 0.0217mg/L in surface water and 0.826mg/L, 0.0415mg/L in bottom water, respectively, which were over III grade of seawater standard. Also high percentage of ammonia nitrogen to DIN in bottom water for autumn and winter was affected by released nutrient from sediment. Correlation analysis of chlorophyll-a versus TSS was shown that organic matter was affected by autochthonous organic matter stem from the algae, these factor showed reverse correlation about salinity. Closely correlations among to the water quality constituent in continuity survey was appeared. The results of eutrophication index estimation showed the high potentiality of red tide occurrence in Shiwha lake, particularity in summer or fall. Overall water quality was greatly improve to compared with measuring data during 1997~1998 at the beginning water gate operation, which reported by KORDI. Therefore, to improve of water quality in Shiwha lake, we need to establish of management plan about nutrient release from sediment, rainfall runoff, maximum of seawater exchange.