• Transactions on Electrical and Electronic Materials
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• v.16 no.3
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• pp.156-161
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• 2015

In this paper, we present simulation results obtained using SILVACO TCAD tools for a 3-D silicon on insulator (SOI) n-FinFET structure with a gate length of 8 nm at 300K. The effects of variations of the device’s key electrical parameters, such as threshold voltage, subthreshold slope, transconductance, drain induced barrier lowering, oncurrent, leakage current and on/off current ratio are presented and analyzed. We will also describe some simulation results related to the influence of the gate work function variations on the considered structure. These variations have a direct impact on the electrical device characteristics. The results show that the threshold voltage decreases when we reduce the gate metal work function Φ_m. As a consequence, the behavior of the leakage current improves with increased Φ_m. Therefore, the short channel effects in real 3-D FinFET structures can reasonably be controlled and improved by proper adjustment of the gate metal work function.

• Journal of Electrical Engineering and Technology
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• v.4 no.3
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• pp.401-404
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• 2009

A simple analytical expression for a current gain of IGBT is derived in terms of the device parameters as well as a gate length dependent parameter, which allows for the determination of the current components of the device as a function of its gate length. The analytical results are compared with those from simulation results. A good agreement is found.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2079-2088
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• 2014

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

• Journal of the Korea Computer Industry Society
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• v.6 no.5
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• pp.783-790
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• 2005

In this paper, we have simulated a Symmetric Dual-gate Single-Si TFT which has three split floating n+ zones. This structure reduces the kink-effect drastically and improves the on-current. Due to the separated floating n+ zones, the transistor channel region is split into four zones with different lengths defined by a floating n+ region, This structure allows an effective reduction of the kink-effect depending on the length of two sub-channels. The on-current of the proposed dual-gate structure is 0.9mA while that of the conventional dual-gate structure is 0.5mA at a 12V drain voltage and a 7V gate voltage. This result shows a 80% enhancement in on-current. Moreover we observed the reduction of electric field in the channel region compared to conventional single-gate TFT and the reduction of the output conductance in the saturation region. In addition, we also confirmed the reduction of hole concentration in the channel region so that the kink-effect reduces effectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.2
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• pp.142-147
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• 2021

We present a subthreshold swing model for a symmetric junctionless double gate MOSFET. The scale length λ1 required to obtain the potential distribution using the Poisson's equation is a criterion for analyzing the short channel effect by an analytical model. In general, if the channel length Lg satisfies Lg > 1.5λ1, it is known that the analytical model can be sufficiently used to analyze short channel effects. The scale length varies depending on the channel and oxide thickness as well as the dielectric constant of the channel and the oxide film. In this paper, we obtain the scale length for a constant permittivity (silicon and silicon dioxide), and derive the relationship between the scale length and the channel length satisfying the error range within 5%, compared with a numerical method. As a result, when the thickness of the oxide film is reduced to 1 nm, even in the case of Lg < λ1, the analytical subthreshold swing model proposed in this paper is observed to satisfy the error range of 5%. However, if the oxide thickness is increased to 3 nm and the channel thickness decreased to 6 nm, the analytical model can be used only for the channel length of Lg > 1.8λ1.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.1-6
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• 2004

Effective gate resistance, extracted by direct extraction method, is analyzed among various gate length, in nanoscale MOSFET for RFIC. Extracted effective gate resistance is compared to measured data and verified with simplified model. Extracted parameters are accurate to 10GHz. In the same process technology effect has a different kind of gate voltage dependency and frequency dependency compared with general effective gate resistance. Particularly, the characteristic of effective gate resistance before and after threshold voltage is noticeable. When gate voltage is about threshold voltage, effective gate resistance is abnormally high. This characteristic will be an important reference for RF MOSFET modeling using direct extraction method.

• Journal of The Korean Society of Agricultural Engineers
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• v.54 no.3
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• pp.133-139
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• 2012

Dynamic characteristic of lift gate supported by plane truss is studied by a model test scaled with the ratio of 1 : 31.25 in the four major rivers project. The vibrations of gate supported by the plane truss is assessed in comparison with those of gate supported by the space truss which was tested formerly. The gate model is made of acryl panel and calibrated by lead. A model test is conducted under the different gate opening and upstream water levels conditions in the concrete test flume dimensioned 1.6 m in width, 0.8 m in height and 24 m in length. In order to verify the model, natural frequencies of the model gate are measured, and compared with the numerical results. The vibrations of gate model supported by the plane truss in opening height of 1.0 cm~2.0 cm shows greater than one supported by the space truss. It is found that the gate model supported by the plane truss is less desirable than one supported by the space truss. thus, the latter type of gate model is requested to design.

• Journal of information and communication convergence engineering
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• v.9 no.6
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• pp.738-742
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• 2011

This paper has studied drain induced barrier lowering(DIBL) for Double Gate MOSFET(DGMOSFET) using analytical potential model. Two dimensional analytical potential model has been presented for symmetrical DGMOSFETs with process parameters. DIBL is very important short channel effects(SCEs) for nano structures since drain voltage has influenced on source potential distribution due to reduction of channel length. DIBL has to be small with decrease of channel length, but it increases with decrease of channel length due to SCEs. This potential model is used to obtain the change of DIBL for DGMOSFET correlated to channel doping profiles. Also device parameters including channel length, channel thickness, gate oxide thickness and doping intensity have been used to analyze DIBL.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.130-133
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• 2011

A comparative study of two capacitance methods to measure the effective channel length in deep-submicron MOSFETs has been made in detail. Since the reduction of the overlap capacitance in the accumulation region is smaller than the addition of the inner fringe capacitance at zero gate voltage, the capacitance method removing the parasitic capacitance in the accumulation region extracts a more accurate effective channel length than the method removing that at zero gate voltage.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.347-350
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• 2004

The substrate parameters of Si MOSFET equivalent circuit model were directly extracted from measured S-Parameters in the GHz region by using simple 2-port parameter equations. Using the above extract ion method, bias and gate length dependent curves of substrate parameters in the RF region are obtained by varying drain voltage at several short channel devices with various gate lengths. These extract ion data will greatly contribute to scalable RF nonlinear substrate modeling.