• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.289.2-289.2
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• 2016

In-Ga-Zn-O(IGZO) receive great attention as a channel material for thin film transistors(TFTs) as next-generation display panel backplanes due to its superior electrical and physical properties such as a high mobility, low off-current, high sub-threshold slope, flexibility, and optical transparency. For the purpose of fabricating high performance IGZO TFTs, a thermal recovery process above a temperature of $300^{\circ}C$ is required for recovery or rearrangement of the ionic bonding structure. However diffused metal atoms from source/drain(S/D) electrodes increase the channel conductivity through the oxidation of diffused atoms and reduction of $In_2O_3$ during the thermal recovery process. Threshold voltage ($V_{TH}$) shift, one of the electrical instability, restricts actual applications of IGZO TFTs. Therefore, additional investigation of the electrical stability of IGZO TFTs is required. In this paper, we demonstrate the effect of Ti diffusion and modulation of interface traps by carrying out an annealing process on IGZO. In order to investigate the effect of diffused Ti atoms from the S/D electrode, we use secondary ion mass spectroscopy (SIMS), X-ray photoelectron spectroscopy, HSC chemistry simulation, and electrical measurements. By thermal annealing process, we demonstrate VTH shift as a function of the channel length and the gate stress. Furthermore, we enhance the electrical stability of the IGZO TFTs through a second thermal annealing process performed at temperature $50^{\circ}C$ lower than the first annealing step to diffuse Ti atoms in the lateral direction with minimal effects on the channel conductivity.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.3
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• pp.41-47
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• 1999

Ion implanted GaAs MESFET with low resistive layer was fabricated using Si diffusion into GaAs from SiN. During the thermal annealing at 95$0^{\circ}C$ for 30s, Si diffused into ion implanted region of GaAs from SiN and they formed low resistive layer of 350$\AA$ thickness. The diffusion of Si decreased the sheet resistance of source and drain region from 1000$\Omega$/sq. to 400$\Omega$/sq. and the AuGe/Ni/Au ohmic contact resitivity from 2.5$\times$10sub -6$\Omega$-cmsup 2 to $1.5\times$10sup -6$\Omega$-cmsup 2. The fabricated lum gate length MESFET with Si diffused surface layer shows the transconductance of 360ms/mm, 8.5dB of associated gain and 3.57dB of minimum noise figure at 12GHz. These performances are better than that of MESFET without Si diffused layer.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.8
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• pp.752-758
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• 2004

This paper reports on the DC and RF characteristics of AlGaN/InGaN/GaN high electron-mobility transistors (HEMTs) grown by molecular beau epitaxy(MBE) on sapphire substrates. The devices with a 0.5 ${\mu}$m gate-length exhibited relatively flat transconductance(g$\_$m/), which results from the enhanced carrier confinement of the InGaN channel. The maximum drain current was 880 mA/mm with a peak g$\_$m/ of 156 mS/mm, an f$\_$T/ of 17.3 GHz, and an f$\_$MAX/ or 28.7 GHz. In addition to promising DC and RF results, pulsed I-V and current-switching measurements showed little dispersion in the unpassivated AlGaN/InGaN HEMTs. These results suggest that the addition of In to the GaN channel improves the electron transport characteristics as well as suppressing current collapse that is related to the surface trap states.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.7 s.110
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• pp.659-664
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• 2006

This paper reports a high power 60 GHz push-push oscillator fabricated using $0.12{\mu}m$ metamorphic high electron-mobility transistors(mHEMTs). The devices with a $0.12{\mu}m$ gate-length exhibited good DC and RF characteristics such as a maximum drain current of 700 mA/mm, a peak gm of 660 mS/mm, an $f_T$ of 170 GHz, and an $f_{MAX}$ of more than 300 GHz. By combining two sub-oscillators having $6{\times}50{\mu}m$ periphery mHEMT, the push-push oscillator achieved a 6.3 dBm of output power at 59.5 GHz with more than - 35 dBc fundamental suppression. The phase noise of - 81.5 dBc/Hz at 1 MHz offset was measured. This is one of the highest output power obtained using mHEMT technology without buffer amplifier, and demonstrates the potential of mHEMT technology for cost effective millimeter-wave commercial applications.

• Proceedings of the Korea Water Resources Association Conference
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• 2005.05b
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• pp.1031-1035
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• 2005

조력발전 건설사업에서 우선적으로 고려되어야 할 사항은 조수간만에 의해 외해부와 조지부 사이를 이동하는 해수를 적절히 소통시키는 것이다. 즉, 조력발전소에서 수문구조물의 목적은 주어진 조건 하에서 계획된 유량을 충분히 그리고 안전하게 배제시키는 것이다. 본 연구에서는 수문구조물에 대한 Apron의 길이와 경사의 변화에 의한 외해 조위와 시화호 수위차 조건에 따른 유량계수를 구해 배수능력과 유$\cdot$출입부, 외해, 시화호 및 큰가리섬 주위의 흐름 특성을 검토하고자 하였다. 이를 위해 시화호를 실험대상으로 하여 구조물을 중심으로 외해측으로 1,000m, 시화호측으로 500m, 폭 1,500m의 범위를 선정하였다. 수리모형을 1대50의 축척비로 제작하였다. 표 1은 실험별 Apron과 수문구조물의 제원을 나타내며, 수문구조물은 7기로 이루어졌다. 시화호의 흐름은 관성력과 중력이 지배력이 되며, 이때 상사법칙은 Froude 상사법칙을 적용할 수 있다. 실험III은 실험II에서 Apron의 경사를 1대10에서 1대5로 수정한 실험으로 수위조건은 외해측 -2.530 EL.m이고, 시화호측은 -1.603EL.m이다. 유량계수를 산정하기 위하여 6개 실험조건을 기본계획에서 제시된 수위-조위 조건에서 수위차 및 통수유량을 분배하여 결정하였고 유량계수 산정식에 따라 구조물의 유입부와 유출부에서 유속-면적법에 의해서 유량을 측정하였다. 그리고 국부평면 실험모형에서의 전체적인 해류의 흐름을 분석하기 위해 2차원 유속을 측정하였다. 또한, 유$\cdot$출입부 안정성을 검토하기 위해 Apron 지점과 수문구조물 지점에 3점법으로 유속을 측정하였으며, 색소를 이용하여 유황을 관찰하였다. 시화호와 외해의 수위차가 1.011 m일 때의 전체 수문구조물을 통과하는 유량을 비교한 결과, 실험II 및 실험III의 통과유량은 각각 $10,924m^3/s$ 및 $10,075m^3/s$로서 실험 I의 $2,757m^3/s$에 비해 통수능이 많이 개선되었음을 알 수 있다.

• Korean Journal of Materials Research
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• v.21 no.2
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• pp.115-119
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• 2011

Si Nanowire (NW) field effect transistors (FETs) were fabricated on hard Si and flexible polyimide (PI) substrates, and their electrical characteristics were compared. Si NWs used as channels were synthesized by electroless etching method at low temperature, and these NWs were refined using a centrifugation method to get the NWs to have an optimal diameter and length for FETs. The gate insulator was poly(4-vinylphenol) (PVP), prepared using a spin-coating method on the PI substrate. Gold was used as electrodes whose gap was 8 ${\mu}m$. These gold electrodes were deposited using a thermal evaporator. Current-voltage (I-V) characteristics of the device were measured using a semiconductor analyzer, HP-4145B. The electrical properties of the device were characterized through hole mobility, $I_{on}/I_{off}$ ratio and threshold voltage. The results showed that the electrical properties of the TFTs on PVP were similar to those of TFTs on $SiO_2$. The bending durability of SiNWs TFTs on PI substrate was also studied with increasing bending times. The results showed that the electrical properties were maintained until the sample was folded about 500 times. But, after more than 1000 bending tests, drain current showed a rapid decrease due to the defects caused by the roughness of the surface of the Si NWs and mismatches of the Si NWs with electrodes.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.213-224
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• 2010

An optically controlled silicon MESFET (OPFET) was fabricated by diffusion process to enhance the quantum efficiency, which is the most important optoelectronic device performance usually affected by ion implantation process due to large number of process induced defects. The desired impurity distribution profile and the junction depth were obtained solely with diffusion, and etching processes monitored by atomic force microscope, spreading resistance profiling and C-V measurements. With this approach fabrication induced defects are reduced, leading to significantly improved performance. The fabricated OPFET devices showed proper I-V characteristics with desired pinch-off voltage and threshold voltage for normally-on devices. The peak photoresponsivity was obtained at 620 nm wavelength and the extracted external quantum efficiency from the photoresponse plot was found to be approximately 87.9%. This result is evidence of enhancement of device quantum efficiency fabricated by the diffusion process. It also supports the fact that the diffusion process is an extremely suitable process for fabrication of high performance optoelectronic devices. The maximum gain of OPFET at optical modulated signal was obtained at the frequency of 1 MHz with rise time and fall time approximately of 480 nS. The extracted transconductance shows the possible potential of device speed performance improvements for shorter gate length. The results support the use of a diffusion process for fabrication of high performance optoelectronic devices.

• Journal of Electrical Engineering and Technology
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• v.12 no.6
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• pp.2324-2332
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• 2017

This paper presents the electrical performances of novel AlGaSb/InGaAs heterojunction-based vertical-tunneling field-effect transistor (VTFET). The device performance was investigated in views of the on-state current ($I_{on}$), drain-induced barrier thinning (DIBT), and subthreshold swing (SS) as the gate length ($L_G$) was scaled down. The proposed TFET with a $L_G$ of 5 nm operated with an $I_{on}$ of $1.3mA/{\mu}m$, a DIBT of 40 mV/V, and an SS of 23 mV/dec at a drain voltage ($V_{DS}$) of 0.23 V. The proposed TFET provided approximately 25 times lower DIBT and 12 times smaller SS compared with the conventional $L_G$ of 5 nm TFET. The AlGaSb/InGaAs VTFET showed extremely high scalability and strong immunity against short-channel effects.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.543-543
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• 2013

Thin-film transistors (TFTs) based on oxide semiconductors have been regarded as promising alternatives for conventional amorphous and polycrystalline silicon TFTs. Oxide TFTs have several advantages, such as low temperature processing, transparency and high field-effect mobility. Lots of oxide semiconductors for example ZnO, SnO2, In2O3, InZnO, ZnSnO, and InGaZnO etc. have been researched. Particularly, zinc-tin oxide (ZTO) is suitable for channel layer of oxide TFTs having a high mobility that Sn in ZTO can improve the carrier transport by overlapping orbital. However, some issues related to the ZTO TFT electrical performance still remain to be resolved, such as obtaining good electrical contact between source/drain (S/D) electrodes and active channel layer. In this study, the bottom-gate type ZTO TFTs with staggered structure were prepared. Thin films of ZTO (40 nm thick) were deposited by DC magnetron sputtering and performed at room temperature in an Ar atmosphere with an oxygen partial pressure of 10%. After annealing the thin films of ZTO at $400^{\circ}C$ or an hour, Cu, Mo, ITO and Ti electrodes were used for the S/D electrodes. Cu, Mo, ITO and Ti (200 nm thick) were also deposited by DC magnetron sputtering at room temperature. The channel layer and S/D electrodes were defined using a lift-off process which resulted in a fixed width W of 100 ${\mu}m$ and channel length L varied from 10 to 50 ${\mu}m$. The TFT source/drain series resistance, the intrinsic mobility (${\mu}i$), and intrinsic threshold voltage (Vi) were extracted by transmission line method (TLM) using a series of TFTs with different channel lengths. And the performances of ZTO TFTs were measured by using HP 4145B semiconductor analyzer. The results showed that the Cu S/D electrodes had a high intrinsic field effect mobility and a low effective contact resistance compared to other electrodes such as Mo, ITO and Ti.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.215-216
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• 2013

The silicide is a compound of Si with an electropositive component. Silicides are commonly used in silicon-based microelectronics to reduce resistivity of gate and local interconnect metallization. The popular silicide candidates, CoSi2 and TiSi2, have some limitations. TiSi2 showed line width dependent sheet resistance and has difficulty in transformation of the C49 phase to the low resistive C54. CoSi2 consumes more Si than TiSi2. Nickel silicide is a promising material to substitute for those silicide materials providing several advantages; low resistivity, lower Si consumption and lower formation temperature. Nickel silicide (NiSi) nanowire (NW) has features of a geometrically tiny size in terms of diameter and significantly long directional length, with an excellent electrical conductivity. According to these advantages, NiSi NWs have been applied to various nanoscale applications, such as interconnects [1,2], field emitters [3], and functional microscopy tips [4]. Beside its tiny geometric feature, NW can provide a large surface area at a fixed volume. This makes the material viable for photovoltaic architecture, allowing it to be used to enhance the light-active region [5]. Additionally, a recent report has suggested that an effective antireflection coating-layer can be made with by NiSi NW arrays [6]. A unique growth mechanism of nickel silicide (NiSi) nanowires (NWs) was thermodynamically investigated. The reaction between Ni and Si primarily determines NiSi phases according to the deposition condition. Optimum growth conditions were found at $375^{\circ}C$ leading long and high-density NiSi NWs. The ignition of NiSi NWs is determined by the grain size due to the nucleation limited silicide reaction. A successive Ni diffusion through a silicide layer was traced from a NW grown sample. Otherwise Ni-rich or Si-rich phase induces a film type growth. This work demonstrates specific existence of NiSi NW growth [7].