• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.2
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• pp.77-79
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• 1992

We propose a self-aligned and double recessed technique for GaAs power MESFETs application. The gate length and the wide recess width are defined by a selective removal of the SiN layer using reactive ion etching(RIE) while the depth of the channel is defined by chemical etching of GaAs layers. The threshold voltages and the saturation drain voltage could be sucessfully controlled using this technique. The lateral-etched distance increases with the dry etching time and the source-drain breakdown voltage of MESFET increases up to about 30V at a pinch-off condition. The electrical characteristics of a MESFET with a gate length of 2 x10S0-6Tm and a source-gate spacing of 33 x10S0-6Tm show maximum transconductance of 120 mS/mm and saturation drain current density of 170-190mA/mm at a gate voltage of 0.8V.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.189-192
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• 2001

We have studied fabrication processes that form asymmetric $\Gamma$-gate with a 0.1${\mu}{\textrm}{m}$ gate length in MMIC's(Monolithic Microwave Integrated Circuits). Asymmetric $\Gamma$-gate was fabricated using mixture of PMMA and MCB. Thus pseudomorphic high electron mobility transistor (PHEMT's) with 0.1${\mu}{\textrm}{m}$ gate length was fabricated via several steps such as mesa isolation, metalization, recess, passivation. PHEMT's has the -1.75 V of pinch-off voltage (Vp), 63 mA of drain saturation current(Idss and 363.6 mS/mm of maximum transconductance (Gm) in DC characteristics and current gain cut-off frequency of 106 GHz and maximum frequency of oscillation of 160 GHz in RF characteristics.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.156-163
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• 2008

We proposed a new $p^+/n^+$ gate locally-separated-channel (LSC) bulk FinFET which has vertically formed oxide region in the center of fin body, and device characteristics were optimized and compared with that of normal channel (NC) FinFET. Key device characteristics were investigated by changing length of $n^+$ poly-Si gate ($L_s$), the material filling the trench, and the width and length of the trench at a given gate length ($L_g$). Using 3-dimensional simulations, we confirmed that short-channel effects were properly suppressed although the fin width was the same as that of NC device. The LSC device having the trench non-overlapped with the source/drain diffusion region showed excellent $I_{off}$ suitable for sub-50 nm DRAM cell transistors. Design of the LSC devices were performed to get reasonable $L_s/L_g$ and channel fin width ($W_{cfin}$) at given $L_gs$ of 30 nm, 40 nm, and 50 nm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1648-1653
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• 2006

In this paper, transport characteristics have been investigated using analytical current-voltage model for double gate MOSFET(DGMOSFET). Scaling down to 100nm of gate length for MOSFET can bring about various problems such as a threshold voltage roll-off and increasing off current by tunneling since thickness of oxide is down by 1.fnm and doping concentration is increased. A current-voltage characteristics have been calculated according to changing of channel length,using analytical current-voltage relation. The analytical model has been verified by calculating I-V relation according to changing of oxide thickness and channel thickness as well as channel length. A current-voltage characteristics also have been compared and analyzed for operating temperature. When gate voltage is 2V, it is shown that a current-voltage characteristic in 77K is superior to in room temperature.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.31-35
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• 2020

This study demonstrates metal-oxide based memtransistor device and the gate tunable memristive characteristic using atomic layer deposition (ALD) and ZnO n-type oxide semiconductor. We fabricated a memtransistor device having channel width 70 ㎛, channel length 5 ㎛, back gate, using 40 nm thick ZnO thin film, and measured gate-tunable memristive characteristics at each gate voltage (50V, 30V, 10V, 0V, -10V, -30V, -50V) under humidity of 40%, 50%, 60%, and 70% respectively, in order to investigate the relation between a memristive characteristic and hydrogen doping effect on the ZnO memtransistor device. The electron mobility and gate controllability of memtransistor device decreased with an increase of humidity due to increased electron carrier concentration by hydrogen doping effect. The gate-tunable memristive characteristic was observed under humidity of 60% 70%. Resistive switching ratio increased with an increase of humidity while it loses gate controllability. Consequently, we could obtain both gate controllability and the large resistive switching ratio under humidity of 60%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.5
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• pp.992-997
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• 2016

This paper analyzes the deviation of tunneling current for the ratio of top and bottom gate oxide thickness of short channel asymmetric double gate(DG) MOSFET. The ratio of tunneling current for off current significantly increases if channel length reduces to 5 nm. This short channel effect occurs for asymmetric DGMOSFET having different top and bottom gate oxide structure. The ratio of tunneling current in off current with parameters of channel length and thickness, doping concentration, and top/bottom gate voltages is calculated in this study, and the influence of tunneling current to occur in short channel is investigated. The analytical potential distribution is obtained using Poisson equation and tunneling current using WKB(Wentzel-Kramers-Brillouin). As a result, tunneling current is greatly changed for the ratio of top and bottom gate oxide thickness in short channel asymmetric DGMOSFET, specially according to channel length, channel thickness, doping concentration, and top/bottom gate voltages.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.1-8
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• 2005

The gate length-dependence of cutoff frequency is modeled by using scaling parameter equations of equivalent circuit parameters extracted from measured S-parameters of Nano-scale MOSFETs. It is observed that the modeled cutoff frequency initially increases with decreasing gate length and then the rate of increase becomes degraded at further scale-down. This is because the extrinsic charging time slightly decreases, although the intrinsic transit time greatly decreases with gate length reduction. The new gate length-dependent model will be very helpful to optimize RF performances of Nano-scale MOSFETs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1266-1272
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• 2012

An InGaZnO thin film transistor with different gate lengths and widths have been fabricated and their device degradations with device sizes have been also performed after negative gate bias stress. The threshold voltage and subthreshold swing have been decreased with decrease of gate length. However, the threshold voltages were increased with the decrease of gate lengths. The transfer curves were negatively shifted after negative gate stress and the threshold voltage was decreased. However, the subthreshold swing was not changed after negative gate stress. This is due to the hole trapping in the gate dielectric materials. The decreases of the threshold voltage variation with the decrease of gate length and the increase of gate width were believed due to the less hole injection into gate dielectrics after a negative gate stress.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.163-168
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• 2015

This paper analyzed the deviation of tunneling current for bottom gate voltage of sub-10 nm asymmetric double gate MOSFET. The asymmetric double gate MOSFET among multi gate MOSFET developed to reduce the short channel effects has the advantage to increase the facts to be able to control the channel current, compared with symmetric double gate MOSFET. The increase of off current is, however, inescapable if aymmetric double gate MOSFET has the channel length of sub-10 nm. The influence of tunneling current was investigated in this study as the portion of tunneling current for off current was calculated. The tunneling current was obtained by the WKB(Wentzel-Kramers-Brillouin) approximation and analytical potential distribution derived from Poisson equation. As a results, the tunneling current was greatly influenced by bottom gate voltage in sub-10 nm asymmetric double gate MOSFET. Especially it showed the great deviation for channel length, top and bottom gate oxide thickness, and channel thickness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.6
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• pp.1422-1428
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• 2014

This paper has analyzed threshold voltage roll-off for bottom gate voltages of asymmetric double gate(DG) MOSFET. Since the asymmetric DGMOSFET is four terminal device to be able to separately bias for top and bottom gates, the bottom gate voltage influences on threshold voltage. It is, therefore, investigated how the threshold voltage roll-off known as short channel effects is reduced with bottom gate voltage. In the pursuit of this purpose, off-current model is presented in the subthreshold region, and the threshold voltage roll-off is observed for channel length and thickness with a parameter of bottom gate voltage as threshold voltage is defined by top gate voltage that off-currnt is $10^{-7}A/{\mu}m$ per channel width. As a result to observe the threshold voltage roll-off for bottom gate voltage using this model, we know the bottom gate voltage greatly influences on threshold voltage roll-off voltages, especially in the region of short channel length and thickness.