• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.137-143
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• 2015

A delay-line type time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) is most widely owing due to its simple structure and high conversion rate. However, the delay-line type TDC suffers from nonlinearity error caused by the long delay-line because its time interval measurement range is determined by the length of the used delay line. In this study, a new TDC structure with a shorter delay line by taking a pulse train as an input is proposed for improved time accuracy and efficient use of resources. The proposed TDC utilizes a pulse-train with four transitions and a transition state detector that identifies the used transition among four transitions and prevents the meta-stable state without a synchronizer. With 72 delay cells, the measured resolution and maximum non-linearity were 20.53 ps, and 1.46 LSB, respectively, and the time interval measurement range was 5070 ps which was enhanced by approximately 343 % compared to the conventional delay-line type TDC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.6
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• pp.1099-1103
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• 2007

TFT's have been intensively researched for possible electronic and display applications. Through tremendous engineering and scientific efforts, a-Si:H TFT fabrication process was greatly improved. In this paper, the reason on defects occurring at a-Si:H TFT fabrication process is analyzed and solved, so a-Si:H TFT's yield is increased and reliability is improved. The a-Si:H TFT of this paper is inverted staggered type TFT. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr). We have fabricated a-SiN:H, conductor, etch-stopper and photo-resistor on gate electrode in sequence, respectively. We have deposited n+a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-slower pattern. The NPR layer by inverting pattern of upper Sate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFT made like this has problems at photo-lithography process caused by remains of PR. When sample is cleaned, this remains of PR makes thin chemical film on surface and damages device. Therefor, in order to improve this problem we added ashing process and cleaning process was enforced strictly. We can estimate that this method stabilizes fabrication process and makes to increase a-Si:H TFT's yield.

• The Transactions of the Korea Information Processing Society
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• v.2 no.6
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• pp.857-865
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• 1995

In this paper, a nibble RLE(Run Length Encoding) code for real time compression and decompression of Hanguel bit map font and printer data is proposed. The nibble RLE code shows good compression ratio in complete form Hangeul Myoungjo and Godik style bit map font and printer output bit map data. And two ASICs seperating compression and decompression are designed and simulated on CAD to verify the proposed code. The 0.8 micron CMOS Sea of Gate is used to implement the ASICs in amount of 2, 400 gates, and these are running at 25MHz. Therefore, the proposed code could be implemented with simple hardware and performs 100M bit/sec compression and decomression at maximum, it is good for real time applications.

• Journal of information and communication convergence engineering
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• v.14 no.1
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• pp.40-44
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• 2016

The device coupling between the stacked top/bottom field-effect transistors (FETs) in two types of monolithic 3D inverter (M3INV) with/without a metal layer in the bottom tier is investigated, and then the regime of the thickness T_ILD and dielectric constant ε_r of the inter-layer distance (ILD), the doping concentration N_d (N_a), and length L_g of the channel, and the side-wall length L_SW where the stacked FETs are coupled are studied. When N_d (N_a) < 10¹⁶ cm^-3 and L_SW < 20 nm, the threshold voltage shift of the top FET varies almost constantly by the gate voltage of the bottom FET, but when N_d (N_a) > 10¹⁶ cm^-3 or L_SW > 20 nm, the shift decreases and increases, respectively. M3INVs with T_ILD ≥ 50 nm and ε_r ≤ 3.9 can neglect the interaction between the stacked FETs, but when T_ILD or ε_r do not meet the above conditions, the interaction must be taken into consideration.

• Earthquakes and Structures
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• v.18 no.5
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• pp.625-635
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• 2020

Suspension bridges have the extended in plan configuration which makes them prone to dynamic events like earthquake. The longer span lead to more flexibility and slender of them. So, control systems seem to be essential in order to protect them against ground motion excitation. Tuned mass damper or in brief TMD is a passive control system that its efficiency is practically proven. Moreover, its parameters i.e. mass ratio, tuning frequency and damping ratio can be optimized in a manner providing the best performance. Meta-heuristic optimization algorithm is a powerful tool to gain this aim. In this study, TMD parameters are optimized in different-length suspension bridges in three distinct cases including 3, 4 and 5 TMDs by observer-teacher-learner based algorithm under a complete set of ground motions formed from both near-field and far-field instances. The Vincent Thomas, Tacoma Narrows and Golden Gate suspension bridges are selected for case studies as short, mean and long span ones, respectively. The results indicate that All cases of used TMDs result in response reduction and case 4TMD can be more suitable for bridges in near and far-field conditions.

• Transactions on Electrical and Electronic Materials
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• v.15 no.3
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• pp.149-154
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• 2014

A new CMOS analog design methodology using an independently optimized self-cascode (SC) is proposed. This idea is based on the concept of the dual-workfunction-gate MOSFETs, which are equivalent to SC structures. The channel length of the source-side MOSFET is optimized, to give higher transconductance ($g_m$) and output resistance ($r_{out}$). The highest $g_m$ and $r_{out}$ of the SC structures are obtained by independently optimizing the channel length ratio of the SC MOSFETs, which is a critical design parameter. An operational amplifier (OPAMP) with the proposed design methodology using a standard digital $0.18-{\mu}m$ CMOS technology was designed and fabricated, to provide better performance. Independently $g_m$ and $r_{out}$ optimized SC MOSFETs were used in the differential input and output stages, respectively. The measured DC gain of the fabricated OPAMP with the proposed design methodology was approximately 18 dB higher, than that of the conventional OPAMP.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.8
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• pp.1777-1781
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• 2011

Tosin backplane system design of this study (Backplane) from the HSTL (High-Speed Transceiver Logic) characteristics of the transmit and receive data using the HSPICE simulations and the actual implementation on the FPGA Data transmission characteristics were described by comparing the simulation results. Simulation and measurement criteria for point to point data transmission characteristics of wire length possible to send and receive data about the speed limits were reviewed. Measured point to point connection to send and receive signals at terminal velocity, the factors that affect the electrical noise around the wire length and showed a very important role.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.16-23
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• 2007

For a fully depleted SOI type symmetric double gate MOSFET, a simple expression for the threshold voltage has been derived in a closed-form To solve analytically the 2D Poisson's equation in a silicon body, the two-dimensional potential distribution is assumed approximately as a polynomial of fourth-order of x, vertical coordinate perpendicular to the silicon channel. From the derived expression for the surface potential, the threshold voltage can be obtained as a simple closed-form. Simulation result shows that the threshold voltage is exponentially dependent on channel length for the range of channel length up to $0.01\;[{\mu}m]$.

• Journal of the Korean Society of Radiology
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• v.15 no.5
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• pp.741-748
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• 2021

In this study, we evaluated image quality by changing collimator length and detector thickness using the Geant4 Application for Tomographic Emission (GATE) simulation tool. The gamma camera based on the Cadimium Zinc Telluride (CZT) and NaI detectors is modeled. In addition the images were acquired by setting 1, 2, 3, 4, 5, and 6 cm collimator length and 1, 3, 5, and 7 mm detector thickness using point source and phantom, which is designed by each diameter (4.45, 3.80, 3.15, 2.55 mm) with 447, 382, 317, and 256 Bq. The sensitivity (cps/MBq) for point source, and signal to noise ratio (SNR) and profile for phantom at the 4.45 mm by drwan the region of interests were used for quantitative analysis. Based on the results, the sensitivity according to collimator length is 2.3 ~ 48.6 cps/MBq for CZT detector, and 1.8 ~ 43.9 cps/MBq for NaI detector. The SNR using phantom is 3.6~9.8 for CZT detector, and 2.9~9.5 for NaI detector. As the collimator length is increased, the image resolution is also improved according to profile results based on the CZT and NaI detector. In addition, the senistivity for detector thickness is 0.04 ~ 0.12 cps/MBq for CZT detector, and 0.03 ~ 0.11 cps/MBq. The SNR using phnatom is 7.3~9.8 count for CZT detector, and 5.9~9.5 for NaI detector. As the detector thickness is increased, the image resolution is decreased according to profile results based on the CZT and NaI detector due to scatter ray. In conclusion, we need to set the geometric material such as detector and collimator to acuquire suitable image quality in nuclear medicine.

• Journal of IKEEE
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• v.18 no.3
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• pp.356-361
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• 2014

This paper proposes hardware architecture of HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) binarizer. The proposed binarizer was designed and implemented as an independent module that can be integrated into HEVC CABAC encoder. It generates each bin string of each syntax element in a single cycle. It consists of controller module, TU (truncated unary binarization) module, TR (truncated Rice binarization) module, FL (fixed length binarization) module, EGK (k-th order exp-Golomb coding) module, CALR (coeff_abs_level_remaining) module, QP Delta (cu_qp_delta_abs) module, Intra Pred (intra_chroma_pred_mode) module, Inter Pred (inter_pred_idc) module, and Part Mode (part_mode) module. The proposed binarizer was designed in Verilog HDL, and it was implemented in 45 nm technology. Its operating speed, gate count, and power consumption are 200 MHz, 1,678 gates, and 50 uW, respectively.