• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.107-112
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• 2005

We present an AlGaN/GaN metal-insulator-semiconductor-heterostructure field effect transistor (MIS-HFET) with an $Al_2O_3-HfO_2$ laminated high-k dielectric, deposited by plasma enhanced atomic layer deposition (PEALD). Based on capacitance-voltage measurements, the dielectric constant of the deposited $Al_2O_3-HfO_2$ laminated layer was estimated to be as high as 15. The fabricated MIS-HFET with a gate length of 102 m exhibited a maximum drain current of 500 mA/mm and maximum tr-ansconductance of 125 mS/mm. The gate leakage current was at least 4 orders of magnitude lower than that of the reference HFET. The pulsed current-voltage curve revealed that the $Al_2O_3-HfO_2$ laminated dielectric effectively passivated the surface of the device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.113-119
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• 2005

4H-SiC planar MESFETs were fabricated using ion-implantation on semi-insulating substrate without recess gate etching. A modified RCA method was used to clean the substrate before each procedure. A thin, thermal oxide layer was grown to passivate the surface and then a thick field oxide was deposited by CVD. The fabricated MESFET showed good contact properties and DC/RF performances. The maximum oscillation frequency of 34 GHz and the cut-off frequency of 9.3 GHz were obtained. The power gain was 10.1 dB and the output power of 1.4 W was obtained for 1 mm-gate length device at 2 GHz. The fabricated MESFETs showed the charge trapping-free characteristics and were characterized by the extracted small-signal equivalent circuit parameters.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.217-222
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• 2003

A new two-dimensional analytical model for the potential distribution and drain-induced barrier lowering (DIBL) effect of fully depleted short-channel Silicon-on-insulator (SOI)-MESFET's has been presented in this paper. The two dimensional potential distribution functions in the active layer of the device is approximated as a simple parabolic function and the two-dimensional Poisson's equation has been solved with suitable boundary conditions to obtain the bottom potential at the Si/oxide layer interface. It is observed that for the SOI-MESFET's, as the gate-length is decreased below a certain limit, the bottom potential is increased and thus the channel barrier between the drain and source is reduced. The similar effect may also be observed by increasing the drain-source voltage if the device is operated in the near threshold or sub-threshold region. This is an electrostatic effect known as the drain-induced barrier lowering (DIBL) in the short-gate SOI-MESFET's. The model has been verified by comparing the results with that of the simulated one obtained by solving the 2-D Poisson's equation numerically by using the pde toolbox of the widely used software MATLAB.

• Journal of Sensor Science and Technology
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• v.29 no.4
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• pp.275-278
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• 2020

In this study, we evaluated the temperature-dependent characteristics of homojunction InGaAs vertical Fin-shaped Tunnel Field-Effect Transistors (Fin TFETs), which were fabricated using a novel nano-fin patterning technique in which the Au electroplating and the high-temperature InGaAs dry-etching processes were combined. The fabricated homojunction InGaAs vertical Fin TFETs, with a fin width and gate length of 60 nm and 100 nm, respectively, exhibited excellent device characteristics, such as a minimum subthreshold swing of 80 mV/decade for drain voltage (V_DS) = 0.3 V at 300 K. We also analyzed the temperature-dependent characteristics of the fabricated TFETs and confirmed that the on-state characteristics were insensitive to temperature variations. From 77 K to 300 K, the subthreshold swing at gate voltage (V_GS) = threshold voltage (V_T), and it was constant at 115 mV/decade, thereby indicating that the conduction mechanism through band-to-band tunneling influenced the on-state characteristics of the devices.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.78-91
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• 1998

This paper presents modular design techniques of multiple-valued logic functions about the function decomposition method and input variable management method. The function decomposition method takes avantage of the property of the column multiplicity in a single-column variable partitioning. Due to the increased number of identical modules, we can achieve a simpler circuit design by using a single T-gate, which can eliminate some of the control functions in the module libraty types. The input variable management method is to reduce the complexity of the input variables by proposing the look up table which assign input variables to a code. In this case as the number of sub-functions increase the code-length and the size of the code-assignment table grow. We identify some situations where shard input variables among sub-functions can be further reduced by a simplicication technique. According to the result of adapting this method to a function, we have demonstrated the superiority of the proposed methods which is bing decreased to about 12% of interconnection and about 16% of T-gate numbers compare with th eexisting for th enon-symmetric and irregular function realization.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.149-158
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• 1995

This paper describes the development of a software tool LCD FRAME that may guide the analyzing process for the electrical characteristics and the design procedure for constructing the thin film transistor liquid crystal display(TFT/LCD) packages. LCD FRAME can analyze its electrical characteristics from the TFT/LCD system package configuration, and provide the design variables to meet the user's requirements. These analysis and design procedure can be done in real time according to the model at simplified package level of TFT/LCD. LCD_FRAME is an object-oriented expert system which considers package elements as objects. With this LCD_FRAME software tool, we analyzed the I-V characteristics of a-Si TFT and its signal distortion which has maximum 1.58 $\mu$s delay along the panel scan line of the package containing 480 ${\times}$ 240 pixels. We designed the package structure of maximum 6.35 $\mu$s signal delays and 3360 ${\times}$ 780 pixels, and as a result we showed that the proper structure of 20 $\mu$m scan line width, 60$\mu$m panel TFT gate width and 8 $\mu$m gate length. This LCD_FRAME software tool provides results of the analysis and the design in the form of input files of the SPICE program, text data files, and graphic charts.

• Journal of electromagnetic engineering and science
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• v.17 no.4
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• pp.178-180
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• 2017

This study presents a 2-20 GHz monolithic distributed power amplifier (DPA) using a $0.25{\mu}m$ AlGaN/GaN on SiC high electron mobility transistor (HEMT) technology. The gate width of the HEMT was selected after considering the input capacitance of the unit cell that guarantees decade bandwidth. To achieve high output power using small transistors, a 12-stage DPA was designed with a non-uniform drain line impedance to provide optimal output power matching. The maximum operating frequency of the proposed DPA is above 20 GHz, which is higher than those of other DPAs manufactured with the same gate-length process. The measured output power and power-added efficiency of the DPA monolithic microwave integrated circuit (MMIC) are 35.3-38.6 dBm and 11.4%-31%, respectively, for 2-20 GHz.

• Proceedings of the KIEE Conference
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• 2000.11c
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• pp.446-448
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• 2000

Organic semiconductors based on vacuum-deposited films of fused-ring polycyclic aromatic hydrocarbon have great potential to be utilized as an active layer for electronic and optoelectronic devices. In this study, pentacene thin films and electrode materials were deposited by Organic Molecular Beam Deposition (OMBD) and vacuum evaporation respectively. For the gate dielectric layer, OPTMER PC403 photo acryl (JSR Coporation.) was spin-coated and cured at $220^{\circ}C$. Electrical characteristics of the devices were investigated, where the channel length and width was $50{\mu}m$ and 5 mm. It was found that field effect mobility was $0.039\;cm^2V^{-1}s^{-1}$, threshold voltage was -7 V, and on/off current ratio was $10^6$.

• Journal of the Korean Applied Science and Technology
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• v.18 no.3
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• pp.191-196
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• 2001

Organic semiconductors based on vacuum-deposited films of fused-ring polycyclic aromatic hydrocarbon have great potential to be utilized as an active layer for electronic and optoelectronic devices. In this study, pentacene thin films and electrode materials were deposited by Organic Molecular Beam Deposition (OMBD) and vacuum evaporation respectively. For the gate dielectric layer, photoacryl (OPTMER PC403 from JSR Co.) was spin-coated and cured at $220^{\circ}C$. Electrical characteristics of the device were investigated, where the channel length and width was 50 ${\mu}m$ and 5 mm. It was found that field effect mobility was 0.039 $cm^{2}V^{-1}s^{-1}$, threshold voltage was -8 V, and on/off current ratio was $10^{6}$. Further details will be discussed.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.202-207
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• 1997

Design and fabrication issues for an L-band GaAs Monolithic Microwave Integrated Circuit(MMIC) Voltage Controlled Oscillator(VCO) as a component of Personal Communications Systems(PCS) Radio Frequency(RF) transceiver are discussed. An ion-implanted GaAs MESFET tailored toward low current and low noise with 0.5mm gate length and 300mm gate width has been used as an active device, while an FET with the drain shorted to the source has been used as the voltage variable capacitor. The principal design was based on a self-biased FET with capacitive feedback. A tuning range of 140MHz and 58MHz has been obtained by 3V change for a 600mm and a 300mm devices, respectively. The oscillator output power was 6.5dBm wth 14mA DC current supply at 3.6V. The phase noise without any buffer or PLL was 93dB/1Hz at 100KHz offset. Harmonic balance analysis was used for the non-linear simulation after a linear simulation. All layout induced parasitics were incorporated into the simulation with EEFET2 non-linear FET model. The fabricated circuits were measured using a coplanar-type probe for bare chips and test jigs with ceramic packages.