• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.322-325
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• 2002

In this study, noise figures of 0.3 $\mu\textrm{m}$-GaAs MESFETs are predicted experimentally with different temperatures. Both the noise figure and the gate leakage current are obtained with wide range of temperatures(27$^{\circ}C$∼300$^{\circ}C$). From the results, gate leakage current increases with temperatures. It is expected that gate leakage current contributes directly to the increase of shot noise current. It is therefore highly recommended to apply an accurate noise analysis to the design of the devices and modules at high temperatures. Fini,Uy the relation between the gate currents resulting in the increase of noise and the noise figures of submicron GaAs MESFETs are traced with different temperatures

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.73-76
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• 2020

The physics-based compact gate leakage current noise models in nanoscale MOSFETs are developed in such a way that the models incorporate important physical effects and are suitable for circuit simulators, including QM (quantum-mechanical) effects. An emphasis on the trap-related parameters of noise models is laid to make the models adaptable to the variations in different process technologies and to make its parameters easily extractable from measured data. With the help of an accurate and generally applicable compact noise models, the compact noise models are successfully implemented into BSIM (Berkeley Short-channel IGFET Model) format. It is shown that the noise models have good agreement with measurements over the frequency, gate-source and drain-source bias ranges.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.44-46
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• 2001

Increase of gate leakage current causes decrease of gain and increase of noise. In this paper, gate leakage current of GaAs MESEFTs' has been traced with different temperatures from $27^{\circ}C\;to\;350^{\circ}C$ to obtain the zero voltage saturation current $J_s$ which is critical to the temperature dependency of total current. From the results, thermal leakage current coefficient has been proposed to compensate for the total current due to the thermionic emission, tunneling, generation and/or hole injection.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.11-19
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of $40M{\sim}725MHz$ with a multiplication range of 11023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.148-152
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• 2009

Recent CMOS technology scaling has seriously eroded the bit-line noise immunity of register files due to the consequent increase in active bit-line leakage currents. To restore its noise immunity while maintaining performance, we propose and evaluate a $256{\times}40$-bit register file incorporating dual-$V_t$ bit-lines with a boosted gate overdrive voltage in 65 nm bulk CMOS technology. Simulation results show that the proposed bootsrapping scheme lowers leakage current by a factor of 450 without its performance penalty.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.3
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• pp.110-117
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• 1995

New formulas for the minimum noise figure and the optimum source impedance of microwave FETs are derived using the noise equivalent circuits obtained from the steady-state Nyquist theorem for multi-terminal semiconductor devices. The derived formulas manifest the relationships between the noise sources and the physical parameters of a noise equivalent circuit. Furthermore the formulas can explain the effect of gate leakage current on the minimum noise figure and the optimum source impedance. comparisons with the published experimental data confirm the validity and usability of our formula.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.359-363
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• 2005

The organic insulation devices with MIM (metal-insulator-metal) structures as PVP gate insulation films were prepared for the application of organic thin film transistors (OTFT). The co-polymer organic insulation films were synthesized by using PVP(poly-4-vinylphenol) as solute and PGMEA (propylene glycol monomethyl ether acetate) as solvent. The cross-linked PVP insulation films were also prepared by addition of poly (melamine-co-formaldehyde) as thermal hardener. The leakage current of the cross-linked PVP films was found to be about 300 pA with low current noise. and showed better property in electrical properties as compared with the co-polymer PVP insulation films. In addition, cross-linked PVP insulation films showed better surface morphology (roughness), showing about 0.11${\~}$0.18 nF in capacitance for all PVP film samples.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.47-52
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• 2006

This paper proposes a novel low-power $32bit\times32bit$ multiplier for deep submicron technologies beyond 130nm. As technology becomes small, static power due to leakage current significantly increases, and it becomes comparable to dynamic power. Recently, shutdown method based on MTCMOS is widely used to reduce both dynamic and static power. However, it suffers from severe power line noise when restoring whole large-size functional block. Therefore, the proposed multiplier mitigates this noise by shutting down and waking up sequentially along with pipeline stage. Fabricated chip measurement results in $0.35{\mu}m$ technology and gate-transition-level simulation results in 130nm and 90nm technologies show that it consumes $66{\mu}W,\;13{\mu}W,\;and\;6{\mu}W$ in idle mode, respectively, and it reduces power consumption to $0.04%\sim0.08%$ of active mode. As technology becomes small, power reduction efficiency degrades in the conventional clock gating scheme, but the proposed multiplier does not.