• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2002.05a
• /
• pp.264-267
• /
• 2002

This paper presents the design of a pipelined virtual output queue routing engine for an advanced input-queued ATM switch, which has a serial cross bar structure. The proposed routing engine has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the routing engine and central arbiter using a new request control method that is based on a high-speed shifter. The designed routing engine has been implemented in a field programmable gate array (FPGA) chip with a 77MHz operating frequency, 16$\times$16 switch size, and 2.5Gbps/port speed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2013.10a
• /
• pp.41-44
• /
• 2013

As appearance of high-quality service such as UDTV application, high-speed and high-capacity communication services are required. For this, communication systems increase the data processing speed and use various error correction techniques. In this paper, we implement the Viterbi decoder applied in 1000BASE-T with 4 pairs UTP cable. The minimum operating speed of the Viterbi decoer should be more than 125 MHz because 125 MHz PAM-5 signal is transmitted on each pair of cables in 1000BASE-T. To do this, we implement the decoder by using the pipeline and parallel processing and verify the operation with 125 MHz by using a logic analyzer. Finally, we will show that the decoder recovers the original data for the added random error data.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2013.10a
• /
• pp.350-353
• /
• 2013

In this paper, a hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is proposed. The designed phase calculator, which adopts redundant binary number systems and a pipelined architecture to improve throughput and speed, performs arctangent operation using vectoring mode of DCORDIC algorithm. Fixed-point MATLAB simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by emulating the restoration of virtual 3D data using MATLAB/Simulink and FPGA-in-the-loop verification, and the estimated performance is about 7.5 Gbps at 469 MHz clock frequency.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.13 no.4
• /
• pp.881-886
• /
• 2018

Over the last several decades, the advances in computer engineering technology have led a new paradigm of data-intensive research in the field of scientific applications. A collaborative work environment for storing, sharing and analyzing data is required for researchers of geographical distance. The Korean government supports the Research & Education network(KREONET) and the Global Science experimental Data hub Center(GSDC) to strengthen the nation's competitiveness. The KREONET has upgraded its backbone to 100Gbps to accommodate demand to transfer data fast among the global major experimental sites. This paper introduces the test result between high performance nodes reserved for big data transfer.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.10a
• /
• pp.780-783
• /
• 2010

Net residual dispersion (NRD) available to transmit RZ formats with different 24 wavelength as a function of duty cycles of RZ format and residual dispersion per span (RDPS) is induced by controlling precompensation only in 960 km optical transmission links of single mode fiber (SMF) with inline dispersion management (DM) for compensating of accumulated dispersion. It is confirmed that effective NRD range for different 24 wavelengths is gradually broadening as RDPS is more smaller, and as duty cycle of RZ format is more larger in the same RDPS.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.4
• /
• pp.125-132
• /
• 2015

PCI Express is high-speed point-to-point serial protocol, the system is designed by analysing loss and jitter through Eye Diagram. It is necessarily analyzing high speed serial signals when the PCI Express Gen3 which has 8Gbps physical signal speed is designed especially. This paper deals with topology extraction, channel analysis, extraction of s-parameters and system signal integrity simulation within transceiver buffer models through PCI Express Gen3 server connecting switch system design. Optimal parameters of transmitter buffer equalizer are found through solution space simulation of de-emphasis and preshoot parameters to compensate channel loss.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.9
• /
• pp.1702-1708
• /
• 2007

Dragon Stream Cipher is proposed for software base implementation in the eSTREAM project. Now this stream cipher is selected as a phase 3 focus candidate. Dragon is a new stream cipher contructed using a single word based NIFSR(non-linear feed back shift register) and 128/256 key/IV(Initialization Vector). Dragon is the keystream generator that produce 64bits of keystream. In this paper, we present an implementation of Drag(m stream cipher algorithm in hardware. Finally, the implementation is on Altera FPGA device, EP3C35F672I and the timing simulation is done on Altera's Quartus II. A result of 111MHz maximum clock rate and 7.1Gbps is throughput is obtained from the implementation.

• International Area Studies Review
• /
• v.13 no.1
• /
• pp.103-122
• /
• 2009

The paper is basically designed to investigate any existence of co-movement among foreign exchange market, goods market, and monetary market implemented by relative PPP and interest rate parity. And, rational expectation and GARCH-M model are employed for an empirical application. The result revealed that since the co-movement among the markets is hardly found, an efficiency of foreign exchange market is independent from any shocks from the goods market and the monetary market. Whereas, the exchange rate is strongly effected by a real interest rate parity. To this end, the real interest rate should be a key policy instrument to stabilize the foreign exchange market.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.4A
• /
• pp.573-578
• /
• 2000

This paper presents a noble optical access system using shared laser and LED light sources, which is based on WDM-PON technologies. This system adopts an external modulation of the shared laser sources for high-speed downstream and a direct modulation of the LED sources for low-speed upstream. To split or combine the transmission channels, AWG(Arrayed Wave-guide Grating) devices are used in the optical cable section. The proposed system is attractive for low cost implementation. The laser light sources can share the optical carriers in the downstream scheme. Also, in upstream, the LED sources can afford to make simple of the circuits for controlling light source and of standardization for ONU(Optical Network Unit). The feasibility of the proposed system is demonstrated by several experiments. Our results show that the system operates well at 2.SGbps for downstream and up to 622.08Mbps for upstream.

• Journal of Broadcast Engineering
• /
• v.19 no.5
• /
• pp.726-735
• /
• 2014

In accordance with 4K UHD(Ultra High Definition) LCD television's higher resolution and data expansion, LCD TV had to face problems such as increasing numbers of cables and tangible skews problems among cables. The V-by-One HS is a new interface technology in the path between the image processing IC and timing control (TCON) board. The variable speed from 600 Mbps to 3.75 Gbps effectively meets the requirements of various different pixel rates. In this paper, we use the V-by-One HS interface to illustrate our proposed simulation method of frequency resonance mode and PCB design approach to model the effects of signal integrity for high speed video signal using an IBIS models.