• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.2
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• pp.76-80
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• 2014

Dual-gate PCRAM which unify capacitor-less DRAM and NVM using a PCM instead of a typical SONOS flash memory is proposed as 1 transistor. $VO_2$ changes its phase between insulator and metal states by temperature and field. The front-gate and back-gate control NVM and DRAM, respectively. The feasibility of URAM is investigated through simulation using c-interpreter and finite element analysis. Threshold voltage of NVM is 0.5 V that is based on measured results from previous fabricated 1TPCM with $VO_2$. Current sensing margin of DRAM is 3 ${\mu}A$. PCM does not interfere with DRAM in the memory characteristics unlike SONOS NVM. This novel unified dual-gate PCRAM reported in this work has 1 transistor, a low RESET/SET voltage, a fast write/erase time and a small cell so that it could be suitable for future production of URAM.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.5
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• pp.366-370
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• 2019

In this paper, a single N+ emitter trench gate-type insulated gate bipolar transistor (IGBT) device was studied using T-CAD, in order to achieve a low on-state voltage drop (Vce-sat) and high breakdown voltage, which would reduce power loss and device reliability. Using the simulation, the threshold voltage, breakdown voltage, and on-state voltage drop were studied as a function of the temperature, the length of time in the diffusion process (drive-in) after implant, and the trench gate depth. During the drive-in process, a $20^{\circ}C$ change in temperature from 1,000 to $1,160^{\circ}C$ over a 150 minute time frame resulted in a 1 to 4 V change in the threshold voltage and a 24 to 2.6 V change in the on-state voltage drop. As a result, a 0.5 um change in the trench depth of 3.5 to 7.5 um resulted in the breakdown voltage decreasing from 802 to 692 V.

• Journal of the Korean Society of Radiology
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• v.13 no.3
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• pp.453-458
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• 2019

In this study we analyzed the tendency of the image characteristic by changing filtering factor for the proposed fast non local means (FNLM) noise reduction algorithm with designed Male Adult mesh (MASH) phantom through Geant4 application for tomographic emission (GATE) simulation program. To accomplish this purpose, MASH phantom for human copy was designed through the GATE simulation program. In addition, we acquired degraded image by adding Gaussian noise with a value of 0.005 using the MATALB program in MASH phantom. Moreover, in degraded image, the FNLM noise reduction algorithm was applied by changing the filtering factors, which set to 0.005, 0.01, 0.05, 0.1, 0.5, and 1.0 value, respectively. To quantitatively evaluate, the coefficient of variation (COV), signal to noise ratio (SNR), and contrast to noise ratio (CNR) were calculated in reconstructed images. Results of the COV, SNR and CNR were most improved in image with a filtering factor of 0.05 value. Especially, the COV was decreased with increasing filtering factor, and showed nearly constant values after 0.05 value of the filtering factor. In addition, SNR and CNR were showed that improvement with increasing filtering factor, and deterioration after 0.05 value of the filtering factor. In conclusion, we demonstrated the significance of setting the filtering factor when applying the FNLM noise reduction algorithm in degraded image.

• Journal of Electrical Engineering and Technology
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• v.11 no.3
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• pp.592-601
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• 2016

This paper presents the modeling of insulated-gate bipolar transistor (IGBT) in electromagnetic transients program (EMTP) simulation for the reliable calculation of switching and conduction losses. The conventional approach considering the physical property of switching devices requires many attribute parameters and large computation efforts. In contrast, the proposed method uses the curve fitting and interpolation techniques based on typical switching waveforms and a user-defined component with variable resistances to capture the dynamic characteristics of IGBTs. Therefore, the simulation time can be efficiently reduced without losing the accuracy while avoiding the extremely small time step, which is required in simulation by the conventional method. The EMTP based simulation includes turn-on and turn-off transients of IGBT, saturation state, forward voltage of free-wheeling diode, and reverse recovery characteristics, etc. The effectiveness of proposed modeling for the EMTP simulation is verified by the comparison with experimental results obtained from practical implementation in hardware.

• Journal of IKEEE
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• v.24 no.1
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• pp.194-199
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• 2020

The threshold voltage roll-off for an asymmetric junctionless double gate MOSFET is analyzed according to the top and bottom gate oxide thicknesses. In the asymmetric structure, the top and bottom gate oxide thicknesses can be made differently, so that the top and bottom oxide thicknesses can be adjusted to reduce the leakage current that may occur in the top gate while keeping the threshold voltage roll-off constant. An analytical threshold voltage model is presented, and this model is in good agreement with the 2D simulation value. As a result, if the thickness of the bottom gate oxide film is decreased while maintaining a constant threshold voltage roll-off, the top gate oxide film thickness can be increased, and the leakage current that may occur in the top gate can be reduced. Especially, it is observed that the increase of the bottom gate oxide thickness does not affect the threshold voltage roll-off.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.66-77
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• 2010

Improvement in breakdown voltage ($BV_{ds}$) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length ($L_g$), but due to lithographic limitation, shortening $L_g$ below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate onto the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the $BV_{ds}$ of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in $BV_{ds}$ can be obtained by applying field plates, especially at the drain side. The important parameters affecting $BV_{ds}$ and cut-off frequency ($f_T$) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate, $\Gamma$-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.

• ETRI Journal
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• v.34 no.4
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• pp.633-636
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• 2012

A dynamic analysis of an amorphous silicon (a-Si) thin film transistor liquid crystal display (TFT-LCD) pixel is presented using new a-Si TFT and liquid crystal (LC) capacitance models for a Simulation Program with Integrated Circuit Emphasis (SPICE) simulator. This dynamic analysis will be useful when predicting the performance of LCDs. The a-Si TFT model is developed to accurately estimate a-Si TFT characteristics of a bias-dependent gate to source and gate to drain capacitance. Moreover, the LC capacitance model is developed using a simplified diode circuit model. It is possible to accurately predict TFT-LCD characteristics such as flicker phenomena when implementing the proposed simulation model.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.7
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• pp.848-854
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• 1999

In this paper, we designed and implemented a precise pulse motor controller chip that generates the pulse needed to control step motor, DC servo and AC servo motors. This chip generates maximum pulse output rate of 5Mpps and has the quasi-S driving capability and speed and moving distance override capability during driving. We designed this chip with VHDL and executed a logic simulation and synthesis using Synopsys tool. The pre-layout simulation and post-layout simulation was executed by Compass tool. This chip was produced with 100 pins, PQFP package by 0.8${\mu}{\textrm}{m}$ gate array process and implemented by completely digital logic. We developed the test hardware board of performance and the CAMC(Computer Aided Motor Controller) Agent softwate to test the performance of the pulse motor controller chip produced. CAMC Agent enables user to set parameters needed to control motor with easy GUI(Graphic User Interface) environment and to display the output response of motor graphically.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.116-126
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• 1994

In this paper, the switch-level fault simulator for CMOS circuits with a gate-to-drain/source short fault is implemented. A fault model used in this paper is based on the graphical analysis of the electrical characteristics of the faulty MOS devices and the conversion of the faulty CMOS circuit to the equivalent faulty CMOS inverter in order to find its effect on the successive stage. This technique is very simple and has the increased accuracy of the simulation. The simulation result of the faulty circuit using the implemented fault simulator is compared with the result of the SPICE simulation.

• Journal of Electrical Engineering and Technology
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• v.9 no.1
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• pp.247-253
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• 2014

In this paper, a new two dimensional (2D) analytical modeling and simulation for a Dual Material Double Gate tunnel field effect transistor (DMDG TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunnelling generation rate and thus we numerically extract the tunnelling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.