• ETRI Journal
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• 제42권6호
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• pp.912-921
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• 2020

Quantum-dot cellular automata (QCA) is an alternative complementary metal-oxide-semiconductor (CMOS) technology that is used to implement high-speed logical circuits at the atomic or molecular scale. In this study, an optimal 2-to-4 decoder in QCA is presented. The proposed QCA decoder is designed using a new formulation based on the MV32 gate. Notably, the MV32 gate has three inputs and two outputs, which is equivalent two 3-input majority gates, and operates based on cellular interactions. A multilayer design is suggested for the proposed decoder. Subsequently, a new and efficient 3-to-8 QCA decoder architecture is presented using the proposed 2-to-4 QCA decoder. The simulation results of the QCADesigner 2.0.3 software show that the proposed decoders perform well. Comparisons show that the proposed 2-to-4 QCA decoder is superior to the previously proposed ones in terms of cell count, occupied area, and delay.

• Journal of Electrical Engineering and Technology
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• 제12권5호
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• pp.2014-2020
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• 2017

A compact current model applicable to both single-gate (SG) and double-gate (DG) tunneling field-effect transistors (TFETs) is presented. The model is based on Kane's band-to-band tunneling (BTBT) model. In this model, the well-known and previously-reported quasi-2-D solution of Poisson's equation is used for the surface potential and length of the tunneling path in the tunneling region. An analytical tunneling current expression is derived from expressions of derivatives of local electric field and surface potential with respect to tunneling direction. The previously reported correction factor with three fitting parameters, compensating for superlinear onset and saturation current with drain voltage, is used. Simulation results of the proposed TFET model are compared with those from a technology computer-aided-design (TCAD) simulator, and good agreement in all operational bias is demonstrated. The proposed SG/DG-TFET model is developed with Verilog-A for circuit simulation. A TFET inverter is simulated with the Verilog-A SG/DG-TFET model in the circuit simulator; the model exhibits typical inverter characteristics, thereby confirming its effectiveness.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권4호
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• pp.462-470
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• 2015

In this study, we analyze the impacts of the trapezoidal fin shape of a double-gate FinFET on the electrical characteristics of circuits. The trapezoidal nature of a fin body is generated by varying the angle of the sidewall of the FinFET. A technology computer-aided-design (TCAD) simulation shows that the on-state current increases, and the capacitance becomes larger, as the bottom fin width increases. Several circuit performance metrics for both digital and analog circuits, such as the fan-out 4 (FO4) delay, ring oscillator (RO) frequency, and cut-off frequency, are evaluated with mixed-mode simulations using the 3D TCAD tool. The trapezoidal nature of the FinFET results in different effects on the driving current and gate capacitance. As a result, the propagation delay of an inverter decreases as the angle increases because of the higher on-current, and the FO4 speed and RO frequency increase as the angle increases but decrease for wider angles because of the higher impact on the capacitance rather than the driving strength. Finally, the simulation reveals that the trapezoidal angle range from $10^{\circ}$ to $20^{\circ}$ is a good tradeoff between larger on-current and higher capacitance for an optimum trapezoidal FinFET shape.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.245-251
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• 2013

The effect of band-to-band tunneling (BTBT) leads to an obvious increase of the leakage current of junctionless (JL) transistors in the OFF state. In this paper, we propose an effective method to decline the influence of BTBT with the example of n-type double gate (DG) JL metal-oxide-semiconductor field-effect transistors (MOSFETs). The leakage current is restrained by changing the geometrical shape and the physical dimension of the gate of the device. The optimal design of the JL MOSFET is indicated for reducing the effect of BTBT through simulation and analysis.

• 산업경영시스템학회지
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• 제35권4호
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• pp.179-185
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• 2012

When manufacturing die casting mold, generally, the casting layout design should be considered based on the relation among injection system, casting condition, gate system, and cooling system. Also, the extent or the location of product defects was differentiated according to the various relations of the above conditions. In this research, in order to optimize casting design of an automobile part (Gear Box) Computer Aided Engineering (CAE) was performed by using the simulation software (Z Cast). The simulation results were analyzed and compared with experimental results. During the mold filling, internal porosities caused by air entrap were predicted and reduced remarkably by the modification of the gate system and the configuration of overflow. With the solidification analysis, internal porosities caused by the solidification shrinkage were predicted and reduced by the modification of the gate system. For making a better production die casting tool, cooling systems on several thick areas are proposed in order to reduce internal porosities caused by the solidification shrinkage.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.96-99
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• 2014

In high-${\kappa}$/metal-gate (HK/MG) metal-oxide-semiconductor field-effect transistors (MOSFETs) at 45-nm and below, the metal-gate material consists of a number of grains with different grain orientations. Thus, Monte Carlo (MC) simulation of the threshold voltage ($V_{TH}$) variation caused by the workfunction variation (WFV) using a limited number of samples (i.e., approximately a few hundreds of samples) would be misleading. It is ideal to run the MC simulation using a statistically significant number of samples (>~$10^6$); however, it is expensive in terms of the computing requirement for reasonably estimating the WFV-induced $V_{TH}$ variation in the HK/MG MOSFETs. In this work, a simple matrix model is suggested to implement a computing-inexpensive approach to estimate the WFV-induced $V_{TH}$ variation. The suggested model has been verified by experimental data, and the amount of WFV-induced $V_{TH}$ variation, as well as the $V_{TH}$ lowering is revealed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.134-142
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• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

• 대한기계학회논문집A
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• 제33권8호
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• pp.793-798
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• 2009

In this paper, the simulation and optimization of SRH (Surface Relief Hologram) masks for printing LCD gate patterns using TIR (Total Internal Reflection) holographic lithography was investigated. A simulation and optimization algorithm based on SDTA (Scalar Diffraction Theory Analysis) method was developed. The accuracy of the algorithm was compared to that of the RCWA (Rigorous Coupled Wave Analysis) method for estimating the Fresnel diffraction pattern of Cr amplitude masks for the given system geometry. In addition, the results from the optimization algorithm were validated experimentally. It was found that one to the most important conditions for the fabrication of SRH masks is to avoid nonlinear shape distortions of the resulting grating. These distortions can be avoided by designing SRH masks with recorded gratings having small aspect ratios of width versus depth. The optimum gap size between the Cr and SRH masks was found using the optimization algorithm. A printed LCD gate pattern with a minimum line width of $1.5{\mu}m$ exposed using the optimized SRH mask was experimentally demonstrated.

• 한국진공학회지
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• 제12권3호
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• pp.182-192
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• 2003

밀리미터파 대역용 고속 PHEMT 소자 제작 및 개발을 위하여 다층 리지스트 및 다원자 기판 구조에서 전자빔 리소그래피 공정을 분석할 수 있는 새로운 몬테 카를로 시뮬레이션 모델을 개발하였다. 전자빔에 의해 다층 다원자 타겟 기판 구조에 전이되는 에너지를 정확하고 효율적으로 계산하기 위하여 다층 리지스트 및 다층 다원자 기판 구조에서 시뮬레이션 가능하도록 새로이 모델링하였다. 본 논문에서 제안 개발된 모델을 사용하여 PHEMT 소자의 전자빔 리소그래피에 의한 T-게이트 형성 공정을 시뮬레이션하고 SEM측정 결과와 비교 분석하여 타당성을 검증하였다.

• 대한전자공학회논문지
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• 제27권4호
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• pp.534-540
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• 1990

In this paper the characteristics of submicron gate GaAs MESFET's have been studied using a particle model which takes into account the hot-electron transport phenomena, i.e., the velocity overshoot. \ulcornervalley(<000> direction), L valley (<111>direction), X valley (<100>direction) as the GaAs conduction energy band and optical phonon, acoustic phonon, equivalent intervalley, nonequivalent intervalley scattering as the scattering models, have been considered in this simulation. And the GaAs material and the device simulation have been done by determination of the free flight time, scattering mechanism and scattering angle according to Monte-Carlo algorithm which makes use of a particle model. As a result of the particle simulation, firstly the electron distribution, the potential energy distribution and the situation of electron displacement in 0.6 \ulcorner gate length device have been obtained. Secondly, the cutoff frequency, obtained by this method, is k47GHz which is in good agreement with the calculated result of theory. And the current-voltage characteristics curve which takes account of the buffer layer effect has been obtained. Lastly it has been verified that parasitic current at the buffer layer can be analyzed using channel depth modulation.