• 대한전자공학회논문지SD
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• 제40권9호
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• pp.714-723
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• 2003

아날로그 IC의 signal swing을 증가시키고 노이즈를 감소시키는 효율적이고 기본적인 방법은 fully-differential 회로를 이용하는 것이다. 하지만 differential-mode 신호처리에 영향을 미치는 common-mode 출력 레벨을 안정되도록 하기 위해서는 common-mode feedback (CMFB)회로가 사용되어야 한다. 본 논문에서는 CMFB 구성과 출력 레벨을 안정되도록 하기 위해 사용되는 에러증폭기 회로들의 설계 방법을 기술하고, 트랜지스터들로만 구성된 효율적인 저 증폭도 에러증폭기론 제안한다. 제안된 에러증폭기는 phase margin 증가 및 differential-mode 입력 신호의 swing 폭을 증가시킨다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.683-686
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• 1998

This paper introduces a sigma-delta DAC with a fully-differential current-mode semidigital IFIR postfilter. A proposed fully-differential postfilter exhibits not only an improved SNR(signal-to-noise ratio) but also a reduced opwer dissipation.

• 한국통신학회논문지
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• 제22권4호
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• pp.685-695
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• 1997

In this paper, a new CMOS continuous-time fully-differential current-mode integrator is proposed as a basic building block of the low-voltage high frequency current-mode active filter. The proposed integrator is composed of the CMOS complementary circuit which can extend transconductance of an integrator. Therefore, the unity gain frequency which is determined by a small-signal transconductance and a MOSFET gate capacitance can be expanded by the complementary transconductance of the proposed integrator. And also the magnitude of pole and zero are increased. The unity gain frequency of the proposed integrator is increased about two times larger than that of the conventional continuous-time fully-differential integrator with NMOS-gm. These results are verified by the small signal analysis and the SPICE simulation. As an application circuit of the proposed fully-differential current-mode integrator, the three-pole Chebyshev lowpass filter is designed using 0.8.$\mu$m CMOS processing parameters. SPICE simulation predicts a 3-dB bandwidth of 148MHz and power dissipation of 4.3mW/pole for the three-pole filter with 3-V power supply.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.289-292
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• 2001

A Novel fully-differential bipolar current-controlled current amplifier(CCCA) for electrically tunable circuit design at current-mode signal processing were designed. The CCCA was consisted of fully-differential subtracter and fully-differential current gain amplifier. The simulation result shows that the CCCA has current input impedance of 0.5 Ω and a good linearity. The CCCA has 3-dB cutoff frequency of 20 MHz for the range over bias current 100$mutextrm{A}$ to 20 ㎃. The power dissipation is 3 mW.

• Nuclear Engineering and Technology
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• 제56권4호
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• pp.1532-1537
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• 2024

Time-of-flight (TOF) PET detectors with fast-rise-time scintillators and fast-single photon time resolution silicon photomultiplier (SiPM) have been developed to improve the coincidence timing resolution (CTR) to sub-100 ps. The CTR can be further improved with an optimal bandwidth and minimized electronic noise in the readout circuit and this helps reduce the distortion of the fast signals generated from the TOF-PET detector. The purpose of this study was to develop an ultra-high frequency and fully-differential (UF-FD) readout circuit that minimizes distortion in the fast signals produced using TOF-PET detectors, and suppresses the impact of the electronic noise generated from the detector and front-end readout circuits. The proposed UF-FD readout circuit is composed of two differential amplifiers (time) and a current feedback operational amplifier (energy). The ultra-high frequency differential (7 GHz) amplifiers can reduce the common ground noise in the fully-differential mode and minimize the distortion in the fast signal. The CTR and energy resolution were measured to evaluate the performance of the UF-FD readout circuit. These results were compared with those obtained from a high-frequency and single ended readout circuit. The experiment results indicated that the UF-FD readout circuit proposed in this study could substantially improve the best achievable CTR of TOF-PET detectors.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 A
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• pp.479-482
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• 1993

A fully balanced differential amplifier can achieve high-gain wide-bandwidth characteristics. And also, Offset PSRR, CMRR and Noise performance of that are excellent, but these merits can be achieved only when the architecture holds fully balanced. Commonly, the fully balanced differential amplifier has a common mode feedback(CMFB) circuit in order to maintain the balance. This paper presents improved characteristics of the CMFB circuit and designs the wide-bandwidth CMOS Op-amp. The unity gain bandwidth of this Op-amp is 50MHz with the load capacitor 2pF, and the value of phase margin is $85^{\circ}$.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 F
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• pp.1896-1898
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• 1998

Balanced differential SCF with common-mode reject fully differential SC network is introduced. Through simulation, performance of balanced differential bandpass SCF and its potentiality of practical application is proposed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.349-355
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• 2015

A fully-differential touch-screen sensing architecture is presented to improve noise immunity and also support most multi-touch events minimizing the number of amplifiers and their silicon area. A correlated double sampling function is incorporated to reduce DC offset and low-frequency noises, and a stabilizer circuit is also embedded to minimize inherent transient fluctuations. A prototype of the proposed readout circuit was fabricated in a $0.18{\mu}m$ CMOS process and its differential operation in response to various touch events was experimentally verified. With a 3.3 V supply, the current dissipation was 3.4 mA at normal operation and $140{\mu}A$ in standby mode.

• ETRI Journal
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• 제28권4호
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• pp.486-494
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• 2006

Two current-mode and/or voltage-mode quadrature oscillator circuits each using one fully-differential second-generation current conveyor (FDCCII), two grounded capacitors, and two (or three) grounded resistors are presented. In the proposed circuits, the current-mode quadrature signals have the advantage of high-output impedance. The oscillation conditions and oscillation frequencies are orthogonally (or independently) controllable. The current-mode and voltage-mode quadrature signals can be simultaneously obtained from the second proposed circuit. The use of only grounded capacitors and resistors makes the proposed circuits ideal for integrated circuit implementation. Simulation results are also included.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.137-140
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• 2001

This paper shows an asynchronous comparator circuit for 1.2Gbps signal receiver that converts 1.2Gbps data rate input signals with less than 100㎷ swing to on-chip CMOS compatible voltage levels in a 0.35${\mu}{\textrm}{m}$ CMOS process. Folded-cascode nMOS input stage with source-coupled pMOS input stage cover rail-to-rail input common-mode range. Drastic gain-bandwidth increment due to gain-boosting stage with positive-feedback latch as well as wide input common-mode range make designed circuit be suitable for a fully differential signal receiver. HSPICE simulation results show that worst-case sensitivity is less than 20㎷ and maximum propagation delay is 640-psec. And also we verified 3.97㎽ power consumption with 150㎷ differential swing amplitude at 1.2Gbps.