• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.1
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• pp.175-181
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• 2010

In this paper, we propose a novel hardware architecture for Rate control module for real time full HD video compression. In the proposed architecture, QP is updated by using the rate control algorithm to every the macroblock line(120MB for Full HD, 20MB for CIF image). Since there are many complex arithmetic and floating point arithmetic in rate control algorithm of JM for H.264, it is impossible to process the rate control algorithm using the integer arithmetic CPU core. So we adopted floating point arithmetic unit in our architecture, and implemented the rate control algorithm using the floating unit. With this implemented hardware, the implemented hardware is verified to be operated in real time.

• Journal of the Semiconductor & Display Technology
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• v.8 no.2
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• pp.59-62
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• 2009

In order to check the validation of LC simulation, 0.7 inch LCOS panel in full-HD resolution was fabricated and used for the electro-optical measurement. Compared the measured data with the calculated data, the averaged difference was 1.72% under 0 ~ +6 V bias on pixel electrode. To improve the optical characteristics of full-HD LCOS panel, the planar structure and trench structures (0.1 um, 0.2 um and 0.3 um-in-depth) between adjacent pixels were investigated with LC simulation. The planar structure showed the higher reflectance and faster reflectance-voltage response time than the trench structure. The optical fill factor and contrast ratio of planar structure were also higher than those of trench structures. As compared 1 um-in-depth trench structure resembled to the real structure with the planar structure, the optical fill factor was improved by 1.15% and the contrast ratio was improved by 5.26%. In order to minimize the loss of luminance and contrast ratio, the planar structure need to be applied between adjacent pixels.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.4
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• pp.2363-2369
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• 2014

The DVR system supports multiple cameras and should be able to receive images at 30 frames per channel in real time. Thus, The system is using Full-HD-grade Multiplexer and Hardware compression codec. In this paper, Describing the design and implementation for the 4-channel Full-HD-grade PC-based DVR using FPGA and GPU inside CPU without Multiplexer and Hardware codec. The existing DVR system for Full-HD-grade has drawbacks to acquire images of about only 20 frames per channel in real time. The system to acquire images of multiple channel in real time was designed using FPGA. The software for the system was implemented using Intel Media SDK. At the result of performance evaluation, It was satisfied all for the required conditions. The practicality of the system was confirmed as implementation the system without using hardware compression.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.07a
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• pp.356-357
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• 2012

본 논문에서는 Full-HD 영상에서 사용되는 H264/AVC의 정수 단위 고속 움직임 예측 방법을 제안한다. 제안되는 알고리즘에서는 다중 해상도 고속 움직임 예측 기법에 기반을 두어 두 계층이 각기 탐색된다. 낮은 해상도의 계층에서는 움직임 벡터 예측자를 중심으로 좁은 탐색 영역을 2 단계로 탐색하여 최적의 점을 찾는다. 높은 해상도의 계층에서는 4 단계로 탐색을 하여 탐색점의 개수를 줄인다. 그리고 두 계층에서 각기 구해진 탐색점들의 비용을 비교하여 매크로블록의 최종 움직임 벡터를 구한다. 시뮬레이션 결과에서는 기존의 연구 결과보다 JM을 기준으로 BD-Rate는 1.55 % 높았고, BD-PSNR은 0.05 dB 낮아진데 비해 시간은 63% 만큼 감소하여 높은 속도를 낼 수 있었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.1
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• pp.46-49
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• 2017

In this letter, we investigate the impact of image downsampling on the performance of background subtraction in Full-HD soccer videos. To this end, we evaluated the performance of background subtraction in terms of both accuracy and computational time. Furthermore, for the sake of completeness, we used two different background subtraction methods under the same experimental setup. For the quantitative comparison, we employed the F-measure and FPS(frames per second). We believe that this study serves as a practically useful benchmark for researchers and practitioners in developing a fast background subtraction algorithm adopted for building real-time intelligent soccer video analysis systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1147-1154
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• 2011

Auto exposure (AE) in image signal processor (ISP) controls brightness of input image to the proper brightness when it is too dark or bright. But conventional AEs often fail to get proper brightness since AE controls only average brightness of image. Especially in applications that require object recognition, it cannot be solved the problem by AE of ISP. In this paper proposes Histogram Equalization (HE) processes that is the alternative of AE. It also proposes proper method to realize hardware and compensate HE problems conventional by using simple calculation.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.167-173
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• 2015

This paper presents a study on the Full-HD HEVC(High Efficiency Video Coding) encoder IP(Intellectual Property) design. The designed IP is for HEVC main profile 4.1, and performs encoding with a speed of 60 fps of full high definition. Before hardware and software design, overall reference model was developed with C language, and we proposed a parallel processing architecture for low-power consumption. And also we coded firmware and driver programs relating IP. The platform for verification of developed IP was developed, and we verified function and performance for various pictures under several encoding conditions by implementing designed IP to FPGA board. Compared to HM-13.0, about 35% decrease in bit-rate under same PSNR was achieved, and about 25% decrease in power consumption under low-power mode was performed.

• ETRI Journal
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• v.31 no.6
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• pp.784-794
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• 2009

We present a full HD (1080p) H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external memory access to fetch samples, which degrades the performance of the encoder. A novel approach to fast ME which uses shared multibank memory can solve these problems. The proposed pixel subsampling ME algorithm is suitable for fast motion vector searches for high-quality resolution images. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software, while sustaining the video quality without any conspicuous PSNR loss. The usage amount of shared multibank memory between the coarse ME and fine ME blocks is 93.6%, which saves external memory access cycles and speeds up ME. It is feasible to perform the algorithm at a 270 MHz clock speed for 30 frame/s real-time full HD encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.75-80
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• 2005

We have studied the needs for developing plasma displays with 1080p quality and the possibilities to construct an affordable 42-inch full HD PDP. It seems impossible to get a prototype unless we overcome technical difficulties. First, we should find a way to innovatively improve luminous-efficacy and interconnection problems. At the same time, we should find a way to overcome image quality degradation in single scan.

• Ingenium
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• v.17 no.1
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• pp.30-33
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• 2010