• Journal of the Korean Society of Hazard Mitigation
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• v.10 no.5
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• pp.27-33
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• 2010

In this study, a monotonic loading test to estimate structural capacity of 12 meter long full scale precast pre-stressed concrete beam specimen was performed with a 2,000 kN dynamic actuator. A couple of embedded steel plate was installed at the ends of the beam and specimens were connected to steel girder frame with high tension bolts. Nominal compressive strength of pre-stressed concrete beam and slab were 50 MPa and 24 MPa respectively. Two HD25 tensile steel reinforcements were welded on vertical plate of embedded steel plate. Pre-stressed concrete beam specimen was loaded by displacement control method with a certain loading pattern which was repeated loading and unloading with 10mm increment displacement. About 88.34%, 86.97% and 66.83% of displacement restoration ratios were evaluated at elastic, inelastic and plastic behavior region of specimen respectively.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.106-111
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the parallel operations and SAD unit control using pattern information, the proposed IME instruction supports not only full search algorithm but also other fast search algorithms. The hardware size is 77K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP runs at 160MHz with sixteen PEGs and it can handle 1080p@30 frame in real time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.58-65
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.12
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• pp.2865-2874
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• 2013

Recently, most of movies top-ranked in the box office are screening in Stereoscopic 3D, and the world's leading electronics companies such as Samsung and LG are getting the hots for 3DTV sales. However, each person has different binocular disparity and different viewing distance, and thus he or she feels the severe visual fatigue and headaches if he or she is watching 3D content with the same binocular disparity, which is very different from things he or she feels in the real world. To solve this problem, this paper proposes and implement a 3D rendering system that correct the disparity of 3D content by reflecting binocular distance and viewing distance. Then, the computational complexity is analyzed. Optical-flow and Warping algorithms turn out to consume 732 seconds and 5.7 seconds per frame, respectively. Therefore, a dedicated chip-set for both blocks is strongly required for real-time HD 3D display.

• Journal of Broadcast Engineering
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• v.26 no.5
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• pp.621-642
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• 2021

In this paper, the subjective video quality assessment of the content quality was to examine by the assessors about the three content quality of HD, Up-scaling UHD, 4K UHD Native that is currently broadcasted. The comparative assessment was conducted using three types of TV sets, 55, 65, 75 inches, at a distance of 2.5 meters which is the distance of watching TV in general households. Among the participants who took part in the video quality evaluating experiment and the questionnaire survey, the answering data of the final 169 persons were adopted after removing the data of 4 persons who answered inadequately in the evaluation of the video quality. The effects of gender, preference of program genre, size of TV sets were analyzed statistically using SPSS 25.0 analysis package. In addition to these, the objective video quality assessment through the measuring instrument was performed, and compared with the results of subjective video quality assessment.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.6
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• pp.18-26
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• 2011

Debates concerning the competitive edge of leading 3DTV technology of the shutter glasses (SG) 3D and the film-type patterned retarder (FPR) are flaring up. Although SG technology enables Full-HD 3D vision, it requires complex systems including the sync transmitter (emitter), the sync processor chip, and the LCD lens in the active shutter glasses. In addition, the transferred sync-signal is easily affected by the external noise and a 3DTV viewer may feel flicker-effect caused by cross-talk of the left and right image. The operating current of the sync processor in the 3DTV active shutter glasses is gradually increasing to compensate the sync reconstruction error. The proposed chip is a low-power hardware sync processor based discrete-event SoC(system on a chip) designed specifically for the 3DTV active shutter glasses. This processor implements the newly designed power-saving techniques targeted for low-power operation in a noisy environment between 3DTV and the active shutter glasses. This design includes a hardware pre-processor based on a universal edge tracer and provides a perfect sync reconstruction based on a floating-point timer to advance the prior commercial 3DTV shutter glasses in terms of their power consumption. These two techniques enable an accurate sync reconstruction in the slow clock frequency of the synchronization timer and reduce the power consumption to less than about a maximum of 20% compared with other major commercial processors. This article describes the system's architecture and the details of the proposed techniques, also identifying the key concepts and functions.

• Journal of Broadcast Engineering
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• v.20 no.3
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• pp.388-397
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• 2015

High Efficiency Video Coding (HEVC)/H.265 is a new video coding standard which is known as high compression ratio compared to the previous standard, Advanced Video Coding (AVC)/H.264. Due to achievement of high efficiency, HEVC sacrifices the time complexity. To apply HEVC to the market applications, one of the key requirements is the fast encoding. To achieve the fast encoding, exploiting thread-level parallelism is widely chosen mechanism since multi-threading is commonly supported based on the multi-core computer architecture. In this paper, we implement both the Tile-level parallelism and the Frame-level parallelism for HEVC encoding on multi-core platform. Based on the implementation, we present two approaches in combining the Tile-level parallelism with Frame-level parallelism. The first approach creates the fixed number of tile per frame while the second approach creates the number of tile per frame adaptively according to the number of frame in parallel and the number of available worker threads. Experimental results show that both improves the parallel scalability compared to the one that use only tile-level parallelism and the second approach achieves good trade-off between parallel scalability and coding efficiency for both Full-HD (1080 x 1920) and 4K UHD (3840 x 2160) sequences.

• Journal of IKEEE
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• v.18 no.4
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• pp.485-494
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• 2014

Traffic Sign Recognition(TSR) is an important element in an Advanced Driver Assistance System(ADAS). However, many studies related to TSR approaches only in normal daytime environment because a sign's unique color doesn't appear in poor environment such as night time, snow, rain or fog. In this paper, we propose a new TSR algorithm based on machine learning for daytime as well as poor environment. In poor environment, traditional methods which use RGB color region doesn't show good performance. So we extracted sign characteristics using HoG extraction, and detected signs using a Support Vector Machine(SVM). The detected sign is recognized by a decision tree based on 25 reference points in a Normalized RGB system. The detection rate of the proposed system is 96.4% and the recognition rate is 94% when applied in poor environment. The testing was performed on an Intel i5 processor at 3.4 GHz using Full HD resolution images. As a result, the proposed algorithm shows that machine learning based detection and recognition methods can efficiently be used for TSR algorithm even in poor driving environment.

• Journal of IKEEE
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• v.17 no.4
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• pp.418-427
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• 2013

In this paper, we propose a parallel deblocking filter algorithm for H.264/AVC video standard. The deblocking filter has different filter processes according to boundary strength (BS) and each filter process requires various conditional calculations. The order of filtering makes it difficult to parallelize deblocking filter calculations. The proposed deblocking filter algorithm is performed on PRAGRAM which is a 1-D coarse grained reconfigurable architecture (CGRA). Each filter calculation is accelerated using uni-directional pipelined architecture of PRAGRAM. The filter selection and the conditional calculations are efficiently performed using dynamic reconfiguration and conditional reconfiguration. The parallel deblocking filter algorithm uses 225 cycles to process a macroblock and it can process a full HD image at 150 MHz.

• ETRI Journal
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• v.36 no.2
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• pp.264-270
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• 2014

This paper introduces a novel repetitive delivery scheme for the left and right views in service-compatible (SC) 3D video that provides full backward compatibility to a legacy DTV system while retaining HD 3D visual quality without additional bandwidth or a codec over the legacy broadcasting channel. The proposed SC delivery scheme transmits individual view sequences of a 3D video in interlaced form, that is, a left-view sequence of a 3DTV program to be used repeatedly is transmitted first and stored locally, and the right-view sequence of the 3D program is then transmitted. This paper specifically describes the signaling, synchronization, and storage format methods used to validate the proposed SC delivery scheme. The experiment results show that the proposed SC delivery scheme can be effectively applied for an SC 3DTV service without degrading the DTV quality using only legacy DTV platforms.