• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.5
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• pp.34-42
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• 2002

In this paper, we designed the VLSI array architecture for the high speed processing of the motion estimation used by block matching algorithm. We derived the one dimensional systolic array from the full search block matching algorithm. The data and control signals of the proposed systolic array are passed through adjacent processing element. So proposed architecture has temporal and spatial locality. The I/O ports exists only in the first and last processing elements of the array. This architecture has low pin counts and modular expandability. So the proposed array architecture can be cascaded for different block size and search range.

• ETRI Journal
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• v.37 no.4
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• pp.772-779
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• 2015

This paper presents a power-efficient hardware realization for a motion estimation technique that is based on the full-search block matching algorithm (FSBMA). The considered input is the quarter common intermediate format of digital video. The mean of absolute difference (MAD) is the distortion criteria employed for the block matching process. The conventional architecture considered for the hardware realization of FSBMA is that of the shift register-based 2-D systolic array. For this architecture, a conservative approximation technique is adapted to eliminate unnecessary MAD computations involved in the block matching process. Upon introducing the technique to the conventional architecture, the power and complexity of its implantation is reduced, while the accuracy of the motion vector extracted from the block matching process is preserved. The proposed architecture is verified for its functional specifications. A performance evaluation of the proposed architecture is carried out using parameters such as power, area, operating frequency, and efficiency.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.3
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• pp.41-56
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• 2000

In this paper, we propose a two-stage fast block matching algorithm using the mean absolute error (MAE) of neighbor search point that can reduce the computational complexity to estimate motion vector while the motion estimation error performance is nearly the same as full search algorithm (FSA) In the proposed method, the lower bound of MAE 6at current search point IS calculated using the MAE of neighbor search point And we reduce the computational complexity by performing the block matching process only at the search point that has to be block matched using the lower bound of MAE The proposed algorithm is composed of two stages The experimental results show that the proposed method drastically reduces the computational complexity while the motion compensated error performance is nearly kept same as that of FSA.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.11
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• pp.1417-1423
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• 1995

In this paper, we propose a full-search block-matching algorithm with early retirement, which can be applied to a 1-D systolic array of processing elements (PE's) for fast motion estimation. In the proposed algorithm, a PE is retired when its current accumulated sum is equal to or larger than the current minimum MAD. If all PE's are retired, the MAD calculation is stopped for the current array position and is started for the next one in the search window. Simulation results show that the optimum motion vector is always found with less computation, the total computation cycles for motion estimation are decreased to about 60%, and the power dissipation in the PE's is reduced to about 40-60%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.8
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• pp.1531-1536
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• 2016

In this paper, we propose a fast motion estimation algorithm which is important in performance of video encoding. Even though so many fast algorithms for motion estimation have been published due to its tremendous computational amount of for full search algorithm, efforts for reducing computations in motion estimation still remain. In the paper, we propose an algorithm that reduces unnecessary computations only, while keeping prediction quality the same as that of the full search. The proposed algorithm does not calculate block matching error for each candidate at once to find motion vectors but divides the calculation procedure into several steps and calculates partial sum of block errors. By doing that, we can estimate the minimum error point early and get the enhancement of calculation speed by reducing unnecessary computations. The proposed algorithm uses smaller computations than conventional fast search algorithms with the same prediction quality as full search.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.278-281
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• 2009

In this paper, we propose a fast partial distortion algorithm using normalized dithering matching scan to get uniform distribution of partial distortion which can reduce only unnecessary computation significantly. Our algorithm is based on normalized dithering order matching scan and calibration of threshold error using LOG value for each sub-block continuously for efficient elimination of unlike candidate blocks while keeping the same prediction quality compared with the full search algorithm. Our algorithm reduces about 60% of computations for block matching error compared with conventional PDE (partial distortion elimination) algorithm without any prediction quality, and our algorithm will be useful to real-time video coding applications using MPEG-4 AVC or MPEG-2.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.2
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• pp.126-131
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• 2004

Full search algorithm(FA) provides the best performance but this is usually impractical because of the large number of computations required for large search region. Fast search and conventional Boolean matching algorithms reduce computational complexity and data processing time but this algorithms have disadvantages that is difficult of implementation of hardware because of high control overhead and that is less performance than FA. This paper presents new Boolean matching algorithm, called BCBM(Bit Converted Boolean Matching). Proposed algorithm has performance closed to the FA by Boolean only block matching that may be very efficiently implemented in hardware for real time video communication. Simulation results show that the PSNR of the proposed algorithm is about 0.08㏈ loss than FA but is about 0.96∼2.02㏈ gain than fast search algorithm and conventional Boolean matching algorithm.

• Journal of Korea Multimedia Society
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• v.12 no.4
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• pp.483-491
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• 2009

In this paper, we propose a fast motion estimation algorithm using adaptive elimination of sub-block partial coefficients. The proposed algorithm predicts an adaptive threshold for each sub-block by using relationship of an initial sum of absolute difference(SAD) and a minimum SAD at the current point, and efficiently reduces unnecessary calculation time of the conventional partial distortion elimination(PDE) algorithm with the predicted threshold. Our algorithm reduces about 60% of computations of the conventional PDE algorithm without any degradation of prediction quality compared with the con ventional full search. Additionally, the proposed algorithm can be applied to other fast motion estimation 떠gorithms. the proposed Our proposing algorithm will be useful to real-time video coding applications using MPEG-2 or MPEG-4 AVC standards.

• Journal of the Institute of Convergence Signal Processing
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• v.18 no.2
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• pp.62-67
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• 2017

In this paper, we propose a fast motion estimation algorithm which is important in performance of video encoding. Even though so many fast algorithms for motion estimation have been published due to tremendous computational amount of full search algorithm, efforts for reducing computations of motion estimation still remain. In the paper, we propose an algorithm that reduces unnecessary computations only, while keeping prediction quality the same as that of the full search. The proposed algorithm does not calculate block matching error for each candidate directly to find motion vectors but divides the calculation procedure into several steps and calculates partial sum of block errors for candidates with high priority. By doing that, we can find the minimum error point early and get the enhancement of calculation speed by reducing unnecessary computations. The proposed algorithm uses smaller computations than conventional fast search algorithms with the same prediction quality as the full search algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9A
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• pp.1392-1400
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• 1999

In this paper, we propose a two-stage fast full search algorithm for block motion estimation that produces the same performance to that of full search algorithm (FSA) but with remarkable computation reduction. The proposed algorithm uses the search region subsampling and the difference of adjacent pixels in the current block. In the first stage, we subsample the search region by a factor of 9, and then calculate mean absolute error (MAE) at the subsampled search points. And in the second stage, we reduce the search points that need block matching process by using the lower bound of MAE value at each search Point. We Set the lower bound of MAE value for each search point from the MAE values which are calculated at the first stage and the difference of adjacent pixels in the current block. The experimental results show that we can reduce the computational complexity considerably without any degradation of picture quality.