• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.5
• /
• pp.595-604
• /
• 2016

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

• Structural Engineering and Mechanics
• /
• v.47 no.5
• /
• pp.729-740
• /
• 2013

This paper addresses the structural design of the front end of Siemens ER24 locomotive body. The steel structure of the frontend is replaced with composite. Optimization of the composite lay-up is performed using Genetic Algorithms. Initially an optimized single design for the entire structure is presented. Then a more refined optimum is developed by considering the separate optimization of 7 separate regions of the structure. Significant savings in the weight of the structure are achieved.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.25 no.4
• /
• pp.487-490
• /
• 2014

This paper describes a design of an automotive radar frontend module with taking care of the routing of 77-GHz signals on a printed circuit board including wire-bond and waveguide transitions.

• Journal of the Korea Convergence Society
• /
• v.10 no.3
• /
• pp.395-400
• /
• 2019

The Web environment of the frontend domain is increasingly competitive to preempt the new standard of presentation layer. N-Screen, a service that enables users to seamlessly use one content in various devices in Korea, is competing for market preemption by recognizing it as a core service of the future. In the cloud computing, N-screen is a typical service type. However, most of the frontend research required for groupware in enterprise environments has been limited to responsive web design for the web and native apps for mobile. Gradually, the need for MVC design patterns is increasingly widening in enterprise environments to overcome the cultural differences of companies and to support one source multi-use strategy supporting multiple devices and development productivity. Therefore, in this study, we will analyze and design JPetStore with hybrid application design based on Spring MVC, e-government standard framework environment of next generation web standard, and provide reference model of frontend hybrid apps design in future enterprise environment.

• ETRI Journal
• /
• v.32 no.2
• /
• pp.214-221
• /
• 2010

Radio frequency (RF) subsampling can be used by radio receivers to directly down-convert and digitize RF signals. A goal of a cognitive radio/software defined ratio (CR/SDR) receiver design is to place the analog-to-digital converter (ADC) as near the antenna as possible. Based on this, a band-pass sampling (BPS) frontend for CR/SDR is proposed and verified. We present a receiver architecture based second-order BPS and signal processing techniques for a digital RF frontend. This paper is focused on the benefits of the second-order BPS architecture in spectrum sensing over a wide frequency band range and in multiband receiving without modification of the RF hardware. Methods to manipulate the spectra are described, and reconstruction filter designs are provided. On the basis of this concept, second-order BPS frontends for CR/SDR systems are designed and verified using a hardware platform.

• Korean Journal of Computational Design and Engineering
• /
• v.19 no.4
• /
• pp.402-409
• /
• 2014

Presented in this paper is a scheduling method for semiconductor backend process considering the backward pegging. It is known that the pegging for frontend is a process of labeling WIP lots for target order which is specified by due date, quantity, and product specifications including customer information. As a result, it gives the release plan to meet the out target considering current WIP. However, the semiconductor backend process includes the multichip package and test operation for the product bin portion. Therefore, backward pegging method for frontend can't give the release plan for backend process in semiconductor. In this paper, we suggest backward pegging method considering the characteristics of multichip package and test operation in backend process. And we describe the backward pegging problem using the examples.

• Journal of Internet Computing and Services
• /
• v.24 no.1
• /
• pp.9-15
• /
• 2023

Single-Page Application(SPA) requires data transformation for communication with RESTful API. The Backend for Frontend(BFF) pattern handles this transformation in the server, but there is some problem that increases the number of communication and makes development and distribution difficult. In this study, we propose an architecture that maps the ViewModel of SPA and the model of RESTful API directly in SPA. The proposed architecture automatically generates a mapping model between the RESTful API model and the ViewModel using the OpenAPI specification, which is the document model of the RESTful API. The data transfer component of SPA automatically converts RESTful API data and ViewModel using the created model. As a result of comparison with the existing BFF method through case study, the proposed architecture showed higher development productivity than BFF, and as a result of load tests, it recorded about 6% lower server CPU occupancy compared to BFF.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.181-182
• /
• 2008

In this paper, an cost-effective system architecture is proposed to implement digital predistortion scheme for linearizing the PA amplifing TDD wideband signal. To make digital predistorted signal for compensating nonlinearity of PA, a dedicated ADC and a frequency-down converter are necessary. Proposed scheme is based on the TDD feature that the RF receiver frontend is idle state during the downlink signal processing time and utilize them to make the digital predistorted signal for PA.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.7B
• /
• pp.1081-1090
• /
• 2010

$0.18{\mu}m$ CMOS UHF RFID tag frontend is presented in this paper. Several key components are highlighted: the voltage multiplier based on the threshold voltage terminated circuit, the demodulator using current mode, and the clock generator. For standard compliance, all designed components are under the EPC Global Class-1 Generation-2 UHF RFID protocol. Backscatter modulation uses the pulse width modulation scheme. Overall performance of the proposed tag chip was verified with the evaluation board. Prototype Tag Chip dimension is neary 0.77mm2 ; According to the simulation results, the reader can successfully interrogate the tag within 1.5m. where the tag consumes the power about $71{\mu}W$.

• The Journal of Korean Institute of Next Generation Computing
• /
• v.15 no.4
• /
• pp.18-29
• /
• 2019

A dynamic adaptive streaming server consumes high processor power because it handles a large amount of transcoding operations at a time. For this purpose, multi-processor architecture is mandatory for which effective transcoding task distribution strategies are essential. In this paper, we present the design and implementation details of the transcoding workload distribution schemes at a 2-tier (frontend node and backend node) transcoding server. For this, we implemented four schemes: 1) allocation of transcoding tasks to appropriate back-end nodes, 2) task scheduling in the back-end node and 3) the communication between front-end and back-end nodes. Experiments were conducted to compare the estimated and the actual power consumption in a real testbed to verify the efficacy of the system. It also proved that the system can reduce the load on each node to optimize the power and time used for transcoding.