• Asia pacific journal of information systems
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• v.3 no.1
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• pp.31-53
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• 1993

Computer Aided Software Engineering(CASE) tools are suggested as an automated method for the efficient development of softwares. This study are intended to measure the use level of CASE tools and to provide the meaningful information on the whole software development environment supported by CASE tools. Therefore, the results of a survey on CASE environment in Korea are empirically reported and analyzed. The use of CASE tools is measured; purposes purchasing CASE tools and achievement levels are investigated. Implications from the comparative analysis of the utilization of software engineering methodologies between the CASE user group and the non-user group are described. A proposition is suggested to check the request frequency for program change. Further studies on the reverse engineering, program reuse and the use of CASE tools under distributed processing systems such as client-server environments are suggested.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.22-38
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• 1997

This paper proposes a new VLSI architecture for morphological filters and presents its chip design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architecture by using a feedback loop path to reuse partial results and a decoder/encoder pair to detect maximum/minimum values. In addition, the proposed architecture requires one common architecture for both diltion and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphologica operations. We developed VHDL (VHSIC hardware description language) models, performed logic synthesis using the SYNOPSYS CAD tool. We used the SOG (sea-of-gate) cell library and implemented the actual chip. The total number of gates is only 2,667 and the clock frequency is 30 MHz that meets real-time image processing requirements.

• 한국정보통신설비학회:학술대회논문집
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• 2006.08a
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• pp.43-46
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• 2006

IEEE 802.16 WirelessMAN aiming to broadband wireless access (BWA) is evolving to 4G mobile communication system through the standardization of IEEE 802.16e supporting mobility on existing fixed WirelessMAN system. It is necessary for hand-over to provide seamless data service while MS (Mobile Station) moves to another BS (Base Station). Because the performance of handover affects packet loss or delay of any communications, it must consider low latency handover mechanism in packet based network. In this paper, we describes handover scheme of IEEE 802.16e with the cell edge interference problem and shows the way to solve the problem in frequency reuse one deployment. Our scheme reduces the handover latency and packet loss probability.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.8
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• pp.481-490
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• 2000

This paper analyzes interference power, Erlang capacity, the number of handoff occurrences, and call blocking probability with respect to the cell radius, the soft handoff region, and the mobile's velocity in a CDMA hierarchical cellular system. The microcell cellular system has the higher Erlang capacity than the macrocell cellular system. However, the microcell cellular system, which has a high system capacity through frequency reuse has the call blocking probability higher than macrocell cellular system. Also the interference power and the call blocking probability are decreased with the operation of soft handoff. Therefore, this paper presents the optimization of soft handoff region so as to maximize system's Erlang capacity with the low the call blocking probability according to mobile's velocity in the CDMA hierarchial cellular system.

• Journal of Broadcast Engineering
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• v.7 no.1
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• pp.10-20
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• 2002

In order to fill the gaps in DTV coverage, KBS Technical Research Institute has researched on DTV on-channel repeating systems as well as DTV translators. The on-channel repeater can reuse frequency resources for expanding service coverage. but it has also many restricts in applications for ATSC DTV system. Thiss Paper compares two kinds of DTV on-channel repealer systems and also presents field test results of both systems. From these results, we Infer their characteristics and summarize the conditions and possibilities of the application for our broadcasting networks.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.339-342
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• 2000

This paper presented a FPGA design of SEED, which is the Korea standard 128-bit block cipher. In this work, SEED was designed technology- independently for other applications such as ASIC or core-based designs. Hence in case of changing the target of design, it is not necessary to modify design or need only minor modification to reuse the design. Since SEED algorithm requires a lot of hardware resources, each unit was designed only once and used sequentially. So, the number of gates was minimized and SEED algorithm was fitted in FPGA without additional components. It was confirmed that the rate of resource usage is about 80% in ALTERA 10KE and the SEED design operates in a clock frequency of 131.57 MHz and an encryption rate of 29 Mbps.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.2
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• pp.263-268
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• 2001

This paper analyzes error probability performance adopted the Ray Tracing method efficiently analyzing millimeter wave or optic wave in Inter Vehicle Communication(IVC). Analysis environment analyzed bit error characteristic in 60㎓ band with very powerful to multipath wave, to be large to oxygen absorption and to be good to frequency reuse efficiency. We analyzed bit error characteristic of DS/CDMA system by multi access user in Two-Ray rician channel adopted reflect wave of grand, reflect wave of concrete wall and reflect wave of driving vehicle at side road. Improvement performance is adopted MRC diversity.

• International journal of advanced smart convergence
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• v.10 no.3
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• pp.81-88
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• 2021

This paper proposes two types of subharmonic RF receiver front-end (called LMV) where, in a single stage, quadrature voltage-controlled oscillator (QVCO) is stacked on top of a low noise amplifier. Since the QVCO itself plays the role of the single-balanced subharmonic mixer with the dc current reuse technique by stacking, the proposed topology can remove the RF mixer component in the RF front-end and thus reduce the chip size and the power consumption. Another advantage of the proposed topologies is that many challenges of the direct conversion receiver can be easily evaded with the subharmonic mixing in the QVCO itself. The intermediate frequency signal can be directly extracted at the center taps of the two inductors of the QVCO. Using a 65 nm complementary metal oxide semiconductor (CMOS) technology, the proposed subharmonic RF front-ends are designed. Oscillating at around 2.4 GHz band, the proposed subharmonic LMVs are compared in terms of phase noise, voltage conversion gain and double sideband noise figure. The subharmonic LMVs consume about 330 ㎼ dc power from a 1-V supply.

• ETRI Journal
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• v.44 no.6
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• pp.955-965
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• 2022

A low Earth orbit (LEO) satellite constellation could be used to provide network coverage for the entire globe. This study considers multi-beam frequency reuse in LEO satellite systems. In such a system, the channel is time-varying due to the fast movement of the satellite. This study proposes an efficient power and bandwidth allocation method that employs two linear machine learning algorithms and take channel conditions and traffic demand (TD) as input. With the aid of a simple linear system, the proposed scheme allows for the optimum allocation of resources under dynamic channel and TD conditions. Additionally, efficient projection schemes are added to the proposed method so that the provided capacity is best approximated to TD when TD exceeds the maximum allowable system capacity. The simulation results show that the proposed method outperforms existing methods.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.51-57
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• 2015

In this paper, in order to design the A / D converter with a high resolution of 14 bits or more for the biological signal processing, CMOS delta sigma modulator that is a 1.8V power supply voltage - were designed. we propose a new structure of The fourth order delta-sigma modulator that needs four op amps but we use only two op amps. By using a time -interleaving technique, we can re-construct the circuit and reuse the op amps. Also, we proposed a KT/C noise reduction circuit to reduce the thermal noise from a noisy resistor. We adjust the size of sampling capacitor between sampling time and integrating time, so we can reduce almost a half of KT/C noise. The measurement results of the chip is fabricated using a Magna 0.18um CMOS n-well1 poly 6 metal process. Power consumption is $828{\mu}W$ from a 1.8V supply voltage. The peak SNDR is measured as a 75.7dB and 81.3dB of DR at 1kHz input frequency and 256kHz sampling frequency. Measurement results show that KT/C noise reduction circuit enhance the 3dB of SNDR. FOM of the circuit is calculated to be 142dB and 41pJ / step.