• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.456-458
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• 1997

The phase-lock technique is applied to a three-phase semi-bridge type battery charger system. Using an inner fast dynamic loop, the phase-locked voltage control (PLVC) technique of three-phase semi-bridge converter is proposed to give a frequency synchronism and to reduce the subharmonics due to the unbalance of transformer or power line. To protect the power devices, the two stage soft-start, function with softly locking the phase and softly increasing the current is presented. As limiting the reference voltage of the inner voltage control loop, muti-lock phenomena are removed on the PLVC loop. A current limit function is also proposed to limit the current of battery and converter. The proposed controller is confirmed through experiment results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.811-815
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• 2005

We theoretically studied synchronization of chaotic oscillation in semiconductor lasers with chaotic light injection feed-back induced chaotic light generated from a master semiconductor laser was injected into a solitary slave semiconductor laser. The slave laser subsequently exhibited synchronized chaotic output for a wide parameter range with strong injection and frequency detuning within the injection locking scheme. We also analytically examined chaos synchronization based on a linear stability analysis from the view point of synchronization based on a linear stability analysis from the view point of modulation response of injection locked semiconductor lasers to chaotic light signal.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.3
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• pp.763-770
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• 1996

In this paper, the Single-stage Transmission type Injectiong-Locked Oscillator(STILO) was designed and fabicated for the Active Integrated Phased Array Antenna(AIPAA) system. The STILO, which was designed and fabricated by injection-locked technique and hair-pin resonator, has the same 210MHz frequency tuning range of the Voltage Controlled Oscillator(VCO) used by varactor. The locking bandwidth of STILO with 11.5MHz bandwidth, is much better than that of the Injection-Locked Dielectric Resonator Oscillator(ILDRO), And the STILO has the improved noise characteristics in AM, FM, and PM. This STILO is useful for the AIPAA, the coupled VCO array, an the MMIC structure.

• Journal of the Optical Society of Korea
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• v.2 no.1
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• pp.9-12
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• 1998

Rational harmonic mode-locking of an Er-doped fiber ring laser has been successfully demonstrated up to the 16-th harmonic, of the RF frequency applied to the electro-optic modulator. This is the highest harmonic reported so far to our knowledge.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.520-527
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• 2016

A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a $0.18-{\mu}m$ CMOS process, occupies an active area of $0.19mm^2$ and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pk-pk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2006.05a
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• pp.74-77
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• 2006

A scanned Fabry-Perot(F-P) filter and a Multi-Channel Wavelength Locker(MCWL) were used to interrogate fiber Bragg grating sensor array. When the F-P filter scans over the MCWL which works as a multi-reference the temporal peaks profiles correspond to the locking wavelengths. To solve the linearity, stability, and accuracy problems caused by the nonlinear response of F-P filter, a polynomial fitting algerian was used to calculate the relationship between the peak locations and the wavelengths in all the scanning range. Then from the reflected peaks locations and the best fitting line, the Bragg wavelengths can be obtained. The measurement linearity was greatly enhanced with wavelength resolution of about 4 pm in 10Hz scanning frequency.

• Current Optics and Photonics
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• v.5 no.3
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• pp.289-297
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• 2021

We describe a comb-mode resolving spectroscopic technique by direct time-domain phase correction of unstable interferograms obtained from loosely locked two femtosecond lasers. A low-cost continuous wave laser and conventional repetition rate stabilization method were exploited for locking carrier and envelope phase of interferograms, respectively. We intentionally set the servo control at low bandwidth, resulting in severe interferograms' fluctuation to demonstrate the capability of the proposed correction method. The envelope phase of each interferogram was estimated by a quadratic fit of carrier peaks to correct timing fluctuation of interferograms in the time domain. After envelope phase correction on individual interferograms, we successfully demonstrated 1 Hz linewidth of RF comb-mode over 200 GHz optical spectral-bandwidth with 10-times signal-to-noise ratio (SNR) enhancement compared to the spectrum without correction. Besides, the group delay difference between two femtosecond pulses is successfully estimated through a linear slope of phase information.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.506-517
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• 2015

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.1-12
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• 2020

Handling precise timing in high-speed transceivers has always been a primary design target to achieve better performance. Many different approaches have been tried, and one of those is utilizing the beneficial nature of injection locking. Though the phenomenon was not intended for building integrated circuits at first, its coupling effect between neighboring oscillators has been utilized deliberately. Consequently, the dynamics of the injection-locked oscillator (ILO) have been explored, starting from R. Adler. As many aspects of the ILO were revealed, further studies followed to utilize the technique in practice, suggesting alternatives to the conventional frequency syntheses, which tend to be complicated and expensive. In this review, the historical analysis techniques from R. Adler are studied for better comprehension with proper notation of the variables, resulting in numerical results. In addition, how the timing jitter or phase noise in the ILO is attenuated from noise sources is presented in contrast to the clock generators based on the phase-locked loop (PLL). Although the ILO is very promising with higher cost effectiveness and better noise immunity than other schemes, unless correctly controlled or tuned, the promises above might not be realized. In order to present the favorable conditions, several strategies have been explored in diverse applications like frequency multiplication, data recovery, frequency division, clock distribution, etc. This paper reviews those research results for clock multiplication and data recovery in detail with their advantages and disadvantages they are referring to. Through this review, the readers will hopefully grasp the overall insight of the ILO, as well as its practical issues, in order to incorporate it on silicon successfully.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.259-262
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• 2012

This paper describes a delay-locked loop (DLL) that generates a 64-phase clock with the operating frequency of 125MHz. The proposed DLL use a $4{\times}8$ matrix-based delay line to improve the linearity of a delay line. The output clock with 64-phase is generated by using a CMOS multiplex and a inverted-based interpolator from 32-phase clock which is the output clock of the $4{\times}8$ matrix-based delay line. The circuit for an initial phase lock, which is independent on the duty cycle ratio of the input clock, is used to prevent from the harmonic lock of a DLL. The proposed DLL is designed using a $0.18-{\mu}m$ CMOS process with a 1.8 V supply. The simulated operating frequency range is 40 MHz to 200 MHz. At the operating frequency of a 125 MHz, the worst phase error and jitter of a 64-phase clock are +11/-12 ps and 6.58 ps, respectively.