• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.5C
• /
• pp.726-736
• /
• 2004

In this paper, we proposed a new scalar multiplier structure needed for an elliptic curve cryptosystem(ECC) over the standard basis in GF(2$^{163}$ ). It consists of a bit-serial multiplier and a divider with control logics, and the divider consumes most of the processing time. To speed up the division processing, we developed a new division algorithm based on the extended Euclid algorithm. Dynamic data dependency of the Euclid algorithm has been transformed to static and fixed data flow by a localization technique, to make it independent of the input and field polynomial. Compared to other existing scalar multipliers, the new scalar multiplier requires smaller gate counts with improved processor performance. It has been synthesized using Samsung 0.18 um CMOS technology, and the maximum operating frequency is estimated 250 MHz. The resulting performance is 148 kbps, that is, it takes 1.1 msec to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2001.05a
• /
• pp.214-217
• /
• 2001

This paper presents an implementation methodology of common Rf- integrated PCS base station system which, is capable of providing PCS services for 3 PCS carriers concurrently and wireless system performance evaluation data is shown. We have built up a common PCS base station system using a commonization module, which is consisted of a multi-channel combiner, duplexer, LNA, power divider, feeder line, and a common set of antennas. It was shown that the performance of the system within the total 30MHz PCS frequency range is uniformly acceptable and measured signal quality and coverage are equivalent to that of the individual PCS base station. It is expected that PCS carriers are able to save a huge amount of installation and maintenance expenses by installing and sharing this base station system. This paper forms a groundwork for deploying efficient and economical IMT-2000 network.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.7
• /
• pp.842-849
• /
• 2010

This paper deals with a TT&C circularly polarized turnstile antenna for LEO satellites. The turnstile antenna consists of radiator for radiating power to free-space and power divider for generating circularly polarized wave. we presents a radiator to tolerate in space environments and a power divider to provide flat phase difference at wide bandwidth. The bandwidth of the proposed antenna covers the frequency bands of up- and down-link. The antenna shows wide beamwidth and enhanced axial ratio for unfavorable space environments.

• The KIPS Transactions:PartC
• /
• v.17C no.2
• /
• pp.145-152
• /
• 2010

In this paper, we first propose a fast division algorithm in GF($2^{163}$) using standard basis representation, and then it is mapped into divider for GF($2^{163}$) with iterative hardware structure. The proposed algorithm is based on the binary ExtendedGCD algorithm, and the arithmetic operations for modular reduction are performed within only one "while-statement" unlike conventional approach which uses two "while-statement". In this paper, we use reduction polynomial $f(x)=x^{163}+x^7+x^6+x^3+1$ that is recommended in SEC2(Standards for Efficient Cryptography) using standard basis representation, where degree m = 163. We also have implemented the proposed iterative architecture in FPGA using Verilog HDL, and it operates at a clock frequency of 85 MHz on Xilinx-VirtexII XC2V8000 FPGA device. From implementation results, we will show that computation speed of the proposed scheme is significantly improved than the existing two approaches.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.2
• /
• pp.27-35
• /
• 2016

A Low jitter dual output frequency synthesizer for smart audio devices is described in this paper. It has been fabricated in a 1.8 V Dongbu $0.18-{\mu}m$ CMOS process. Output frequency is controlled by 3 rd order Sigma-Delta Modulation and digital divider. The frequency synthesizer has a size of $0.6mm^2$, frequency range of 0.6-200 MHz, loop bandwidth of 350 kHz, and rms jitter of 11.4 ps-21.6 ps.

• Transactions on Semiconductor Engineering
• /
• v.2 no.3
• /
• pp.1-5
• /
• 2024

This paper presents a crystal-less reference clock recovery (CR) frequency synthesizer with compensation designed for Bluetooth Low Energy (BLE) Smart-tag applications, operating at frequencies of 32, 72, and 80MHz. In contrast to conventional frequency synthesizers, the proposed design eliminates the need for external components. Using a single-ended antenna to receive a minimal input power of -36dBm at a 2.4GHz signal, the CR synthesizes frequencies by processing the RF signal received through a Low Noise Amplifier ( L N A ) . This approach allows the system to generate a reference clock without relying on a crystal. The received signal is amplified by the LNA and then input to a 16-bit ACC (Automatic Clock Compensation) circuit. The ACC compares the frequency of the received signal with the oscillator output signal, using the synthesis of a 32MHz reference clock through a frequency compensation method. The oscillator is constructed using a Ring Oscillator (RO) with a Frequency Divider, offering three different frequencies (32/72/80MHz) for various system components. The proposed frequency synthesizer is implemented using a 55-nm CMOS process.

• Proceedings of the IEEK Conference
• /
• 2002.07a
• /
• pp.341-344
• /
• 2002

This paper is proposed a 8-bit analog to digital converter for CMOS image sensor. A analog to digital converter for CMOS image sensor is required function to control gain. Frequency divider is used In control gain in this proposed analog to digital converter. At 3.3 Volt power supply, total static power dissipation is 8㎽ and programmable gain control range is 30㏈. Newly suggested analog to digital converter is designed by 0.35um 2-poly 4-metal CMOS technology.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.845-848
• /
• 2005

This paper describes a 4.224GHz CMOS charge pump PLL for Mode 1 MB-OFDM UWB hopping carrier generation. It includes a qudrature VCO of which the frequency range is from 3.98GHz to 4.47GHz(@ 0.4 to 1.5 V), a divider, a PFD, a loop filter, a charge pump, and a lock detector. Designed in a 0.18um CMOS technology, the PLL draws 6.6mA from a 1.8V supply. The phase noise of the designed VCO is -133dBc/Hz@3MHz.

• IEIE Transactions on Smart Processing and Computing
• /
• v.4 no.3
• /
• pp.158-162
• /
• 2015

A low phase noise CMOS voltage controlled oscillator(VCO) for multi-band/multi-standard RF Transceivers is presented. For both wide tunability and low phase noise characteristics, Hybrid inductor which uses both bondwire inductor and planar spiral inductor in the same area, is proposed. This approach reduces inductance variation and presents high quality factor without custom-designed single-turn inductor occupying large area, which improves phase noise and tuning range characteristics without additional area loss. An LC VCO is designed in a 0.13um CMOS technology to demonstrate the hybrid inductor concept. The measured phase noise is -121dBc/Hz at 400KHz offset and -142dBc/Hz at 3MHz offset from a 900MHz carrier frequency after divider. The tuning range of about 28%(3.15 to 4.18GHz) is measured. The VCO consumes 7.5mA from 1.3V supply and meets the requirements for GSM/EDGE and WCDMA standard.

• Journal of electromagnetic engineering and science
• /
• v.16 no.4
• /
• pp.241-247
• /
• 2016

This paper proposes the design and measurement of a 6-18 GHz front-end receiver module that has been combined into a one- channel output from a two-channel input for electronic warfare support measures (ESM) applications. This module includes a limiter, high-pass filter (HPF), power combiner, equalizer and amplifier. This paper focuses on the design aspects of reducing the noise figure (NF) and matching the phase and amplitude. The NF, linear equalizer, power divider, and HPF were considered in the design. A broadband receiver based on a combined configuration used to obtain low NF. We verify that our receiver module improves the noise figure by as much as 0.78 dB over measured data with a maximum of 5.54 dB over a 6-18 GHz bandwidth; the difference value of phase matching is within $7^{\circ}$ between ports.