• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.614-617
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• 1999

To achieve high efficiency in high power and high frequency applications, reduction of switching losses and noise is very important. In this paper, an improved zero voltage switching forward dc/dc converter is proposed. The proposed converter is constructed by using energy recovery snubbers in parallel with the main switches and output diodes of the conventional forward dc/dc converter. Due to the use of the energy recovery snubbers in the primary and secondary side, the proposed converter achieves zero-voltage-switching turn-off without switching losses for switching devices and output rectification diodes. The complete operating principles and experimental results will be presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.64-70
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• 2009

A 6-Gbps feed-forward equalizer having a 6.2-dB gain at 3GHz is designed in 0.13-um CMOS technology and the equalizer helps error-free data recovery over a 7-m SATA cable with 14.7dB loss. Based on a differentially-connected varactor, the proposed equalizer uses only a one-fourth varactor size of a conventional equalizer, which enables the equalizer's integration in a pad-frame, high operating frequency, and low power dissipation of 3.6mW.

• Journal of Power Electronics
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• v.9 no.2
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• pp.259-266
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• 2009

In order to increase the power density of power converters, reduction of the switching losses at high-frequency switching conditions is one of the most important issues. This paper presents a new gate drive circuit that enables the reduction of switching losses in both the Power MOSFET and the IGBT. A distinctive feature of this method is that both the turn-on loss and the turn-off loss are decreased simultaneously without using a conventional ZVS circuit, such as the quasi-resonant adjunctive circuit. Experimental results of the switching loss of both the Power MOSFET and the IGBT are shown. In addition, an energy recovery circuit suitable for use in IGBTs that can be realized by modifying the proposed gate drive circuit is also proposed. The effectiveness of both the proposed circuits was confirmed experimentally by the buck-chopper circuit.

• Journal of Power Electronics
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• v.4 no.1
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• pp.39-45
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• 2004

A novel current-fed energy-recovery sustaining driver (CFERSD) for a PDP is proposed in this paper. Its main idea is to recover the energy stored in the PDP or to inject the input source energy to the PDP by using the current source built-up in the energy recovery inductor. This method provides zero-voltage-switching (ZVS) of all main power switches, the reduction of EMI, and more improved operational voltage margins with the aid of the discharge current compensation. In addition, since the current flowing through the energy recovery inductor can compensate the plasma discharge current flowing through the conducting power switches, the current stress through all main power switches can be considerably reduced. Furthermore, it features a low conduction loss and fast transient time. Operations, features and design considerations are presented and verified experimentally on a 1020${\times}$l06mm sized PDP, 50kHz-switching frequency, and sustaining voltage 140V based prototype.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.82-86
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• 2009

This work is design of clock and data recovery circuit using system clock. This circuit is composed by PLL(Phase Locked Loop) to make system clock and data recovery circuit. The data recovery circuit using 1/4-rate phase picking Detector helps to reduce clock frequency. It is advantageous for high speed PLL. It can achieve a low jitter operation. The designed CDR(Clock and data recovery) has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and an active area $1{\times}1mm^2$.

• Korean Journal of Adult Nursing
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• v.18 no.5
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• pp.691-698
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• 2006

Purpose: This research was conducted to evaluate, analyze, and determine the limitation of the anesthesia that is used in there covery room in order to provide the foundation for developing the effectiveness of it. Method: There covery records of this study were collected from 41 hospitals in Seoul, Kyung Kii-Do, and Inchon province. The post anesthetic recovery records consisted of the evaluation of type, evaluative items, frequency, time, score and $SaO_2$. These records were collected from September to December of 2005. Results: The most commonly used post anesthetic evaluation tool was Alderete Score, which was used in 73% of hospitals. The second was Aldrete Score with $SaO_2$(17%). Also, 5% of the hospitals used the modified AS form. There were 2.5% of the hospitals applying the adult and child in the evaluation separately. Also, the last 2.5% of the hospitals did not use AS but measured BP, pulse, respiration, temperature, and $SaO_2$ with observing nausea, vomiting, urinary retention, backache, laryngitis, shock, and neurologic assessment. Conclusion: It is necessary to develop a post-anesthetic recovery evaluation tool including the application of $SaO_2$, so that the early-diagnosis of hypoxia can be possible. In addition, it is necessary to develop a post- anesthetic recovery evaluating method that can distinguish a difference between adults and children.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.10
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• pp.1001-1008
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• 1991

.In this paper the efficient clock recovery algorithm is proposed to regenerate the manchester code at the system using the Manchester encoding scheme such as LAN. Mobile communication and digital communication systems. The proposed clock recovery circuit recovers the clock using the two times of the same original transmitted frequency can be completely recovered. The implementation of the proposed clock recovery circuit and the interpretation of test results prove the validity of the proposed algorithm.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.3
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• pp.214-220
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• 2022

This paper proposes a test device designed for developing a high-voltage multilayer ceramic capacitor (MLCC). The proposed topology consists of an energy recovery circuit for charging/discharging capacitor, a flyback converter, and a boost converter for supplying power and a bias voltage application to the energy recovery circuit. The energy recovery circuit designed with a half-bridge converter has auxiliary switches operating before the main switches to prevent excessive current from flowing to the main switches. A prototype has been designed to verify the reliability of target capacitors following the voltage fluctuation with a frequency range below 65 kHz. To conduct high root mean square (RMS) current to the capacitor as a load, the MLCC test was conducted after the topology verification was completed through the film capacitor as a load. Through the agreement between the RMS current formula proposed in this paper and the MLCC test results, the possibility of its use was demonstrated for high-voltage MLCC development in the future.

• Journal of information and communication convergence engineering
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• v.22 no.2
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• pp.89-97
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• 2024

This research conducted a comparative analysis of two communication systems. The first system utilizes a conventional series configuration consisting of a symbol-rate least mean square (LMS) equalizer followed by a timing recovery loop. The second system introduces an innovative approach that integrates a symbol-rate LMS equalizer and a timing recovery component within a single loop, allowing mutual feedback between the two blocks. In this integrated system, the equalizer also provides timing error information, thereby eliminating the requirement for a separate threshold error detector. This study examines the performance curves of both system configurations. The simulation results revealed that the integrated system may offer improved stability in terms of multiple transmission challenges, including phase and frequency offsets and intersymbol interference. Further analysis and discussion highlight the significant insights and implications of the proposed architecture. Overall, the present findings provide an alternative perspective on the joint implementation of equalization and timing recovery in communication systems.

• Nuclear Engineering and Technology
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• v.54 no.1
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• pp.110-116
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• 2022

Human failure event (HFE) dependency analysis is a part of human reliability analysis (HRA). For efficient HFE dependency analysis, a maximum number of minimal cut sets (MCSs) that have HFE combinations are generated from the fault trees for the probabilistic safety assessment (PSA) of nuclear power plants (NPPs). After collecting potential HFE combinations, dependency levels of subsequent HFEs on the preceding HFEs in each MCS are analyzed and assigned as conditional probabilities. Then, HFE recovery is performed to reflect these conditional probabilities in MCSs by modifying MCSs. Inappropriate HFE dependency analysis and HFE recovery might lead to an inaccurate core damage frequency (CDF). Using the above process, HFE recovery is performed on MCSs that are generated with a non-zero truncation limit, where many MCSs that have HFE combinations are truncated. As a result, the resultant CDF might be underestimated. In this paper, a new method is suggested to incorporate HFE recovery into the MCS generation stage. Compared to the current approach with a separate HFE recovery after MCS generation, this new method can (1) reduce the total time and burden for MCS generation and HFE recovery, (2) prevent the truncation of MCSs that have dependent HFEs, and (3) avoid CDF underestimation. This new method is a simple but very effective means of performing MCS generation and HFE recovery simultaneously and improving CDF accuracy. The effectiveness and strength of the new method are clearly demonstrated and discussed with fault trees and HFE combinations that have joint probabilities.