• Journal of Korean Academy of Fundamentals of Nursing
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• v.6 no.1
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• pp.51-63
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• 1999

This study examined two differences in physical and psychological recovery patterns after surgery in the elderly. The sample consisted of 40 patients with abdominal surgery In five large hospitals in Seoul. The data for this study were collected from Apr. 20 to Nov. 26 by structured questionnaire, chart review and call. Physical recovery was assessed by ADL, a Cantril Ladder Scale and a Visual Analogue Scale. Psychological recovery was measured by the Geriatric depression Scale and a Cantril Ladder Scale. The data were analyzed using frequency, percentage, Pearson Correlation Coefficient, and MANOVA by SPSS/WIN. The result are as follows : 1. Physical recovery indicated significant improvement over time with the exception of ADL(F=.812 p=.449). Perceived physical health were significantly improved(F=6.189 p=.004). Pain & discomfort was significantly decreased(F=3.927 p=.025). 2. Perceived psychological health was significantly improved over time(F=20.648 p=.000), but depression showed no statistical significance improvement over time(F=1.393 p=.256). 3. There were no significant effects of sex, age, complication and combined chronic diseases on physical and psychological recovery patterns. 4. There were significant correlations between operation time and pain(r=-.331 p=.020), recovery time and perceived psychological health(r=-.320 p=.024), recovery time and pain(r=.404 p=.005). There were significant correlations between admision period and ADL(r=-.418 p=.004), perceived physical health(r=-.354 p=.014), depression(r=.280 p=.042), and perceived psychological health(r=-.447 p=.002). BRAS showed significant correlation with ADL(r=-.458 p=.002). 5. With an increase in the degree of perceived health(physical and psychological), ADL was significantly increased. With an increased in the degree of depression and pain, ADL and perceived health(physical and psychological) were significantly decreased. In conclusion, the elderly patient recovered significantly over time with the exception of ADL and depression. It these we suggested to considered when planning care for elderly patients.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.10-15
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• 2006

In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4x oversampling phase and frequency detector structure without a reference clock is described. The phase detector (PD) and frequency detector (FD)are designed by 4X oversampling method. The PD, which uses bang-bang method, finds the phase error by generating four up/down signal and the FD, which uses the rotational method, finds the frequency error by generating up/down signal made by the PD output. And the six signals of the PD and the FD control an amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. Proposed circuit is designed using the 0.18um CMOS technology and operating voltage is 1.8V. With a 4X oversampling PD and FD technique, tracking range of 24% at 3.125Gbps is achieved.

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.1-12
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• 2020

Handling precise timing in high-speed transceivers has always been a primary design target to achieve better performance. Many different approaches have been tried, and one of those is utilizing the beneficial nature of injection locking. Though the phenomenon was not intended for building integrated circuits at first, its coupling effect between neighboring oscillators has been utilized deliberately. Consequently, the dynamics of the injection-locked oscillator (ILO) have been explored, starting from R. Adler. As many aspects of the ILO were revealed, further studies followed to utilize the technique in practice, suggesting alternatives to the conventional frequency syntheses, which tend to be complicated and expensive. In this review, the historical analysis techniques from R. Adler are studied for better comprehension with proper notation of the variables, resulting in numerical results. In addition, how the timing jitter or phase noise in the ILO is attenuated from noise sources is presented in contrast to the clock generators based on the phase-locked loop (PLL). Although the ILO is very promising with higher cost effectiveness and better noise immunity than other schemes, unless correctly controlled or tuned, the promises above might not be realized. In order to present the favorable conditions, several strategies have been explored in diverse applications like frequency multiplication, data recovery, frequency division, clock distribution, etc. This paper reviews those research results for clock multiplication and data recovery in detail with their advantages and disadvantages they are referring to. Through this review, the readers will hopefully grasp the overall insight of the ILO, as well as its practical issues, in order to incorporate it on silicon successfully.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.87-95
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• 2013

In this paper, 2.5 Gb/s burst-mode clock and data recovery(CDR) is presented. Digital frequency calibration scheme is adopted to eliminate mismatch between the input data rate and the output frequency of the gated voltage controlled oscillator(GVCO) in the clock recovery circuitry. A jitter rejection scheme is also used to reduce jitter caused by input data. The proposed burst-mode CDR is designed using 0.11 ${\mu}m$ CMOS technology. Post-layout simulations show that peak-to-peak jitter of the recovered data is 14 ps with 0.1 UI input referred jitter, and maximum tolerance of consecutive identical digit(CID) is 2976 bits without input data jitter. The active area occupies 0.125 $mm^2$ without loop filter and the total power consumption is 94.5 mW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.171-177
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• 2006

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver with the clock-hold function has been designed and implemented. It consists of a clock extractor circuit, an RF mixer and a frequency discriminator for phase/frequency detection, a VC-DRO, a phase shifter, and a clock-hold circuit. The extracted 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module are significantly improved as compared with those of the conventional open-loop type clock recovery module with a DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When an input signal is dropped, the 40 GHz clock is maintained continuously by the hold circuit.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.1
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• pp.56-62
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• 2011

A Satellite transponder is mounted on the Satellite and performs radio communications with the ground station. A Digital transponder compared to The analog transponder is made easy and accurate performance prediction. Also Modulation Scheme, Data Rate, Loop Bandwidth, Modulation Index and etc. can be changed on orbit, by implementing FPGA can reduce the weight and volume. The core technology of digital transponder is Carrier Recovery loop. Dynamic Range, Frequency Tracking Range, Frequency Tracking Rate and Coherent performance are determined by the performance of the Carrier Recovery loop. In this paper, we proposed the structure of Carrier Recovery loop for the Satellite digital transponder, then tested and verified the structure.

• Journal of Advanced Navigation Technology
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• v.19 no.3
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• pp.244-249
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• 2015

High-altitude electromagnetic pulse (HEMP) is generated from a nuclear burst at high altitudes above the Earth, the electromagnetic fields reach the ground nearly simultaneously with regard to the operation time of systems. The aim of this analysis is to inquire about HEMP characteristics and to analyze about effect in orthogonal frequency division multiplexing (OFDM) system. Specifically, HEMP characteristics are classified field sources, spatial coverage, time domain behavior, frequency spectrum and field intensities in this study. Bits error rate (BER) of the receiver with the software simulation is confirmed for the HEMP effect. Q-factor made a difference about interference duration by transfer characteristics of system. When Q factor is smaller, the recovery time from HEMP interference is short. To the contrary, if the Q factor is larger, the recovery duration is lasted longer by 300-600%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1436-1444
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• 2000

In this paper, we propose the joint carrier and symbol timing recovery algorithm using repetitive preamble and differential detection for burst modem. The proposed algorithm can estimate the frequency offset and the symbol timing error regardless of the amount of frequency offset, with a high accuracy, even using very short preamble and at low SNR values. The algorithms for continuous phase frequency shift keying (CPFSK) and phase shift keying (PSK) types are developed. Through computer simulations, we compare the proposed algorithm with the existing algorithms on the estimation accuracy in terms of the preamble length, and analyze those bit error rate(BER) performance.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.755-760
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• 2003

A novel current-fed energy-recovery sustaining driver (CFERSD) for a PDP is proposed in this paper. Its main idea is to recover the energy stored in the PDP or to inject the input source energy to the PDP by using the current source built-up in the energy recovery inductor. This method provides zero-voltage-switching (ZVS) of all main power switches, the reduction of EMI, and more improved operational voltage margins with the aid of the discharge current compensation. In addition, since the current flowing through the energy recovery inductor can compensate the plasma discharge current flowing through the conducting power switches, the current stress through all main power switches can be considerably reduced. Furthermore, it features a low conduction loss and fast transient time. Operations, features and design considerations are presented and verified experimentally on a 1020X106mm sized PDP, 50kHz-switching frequency, and sustaining voltage 140V based prototype.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.189-191
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• 2018

This paper introduces a novel ZVS interleaved totem-pole PFC with the reduced circulating current and the reverse recovery current of the diodes. With the help of a simple auxiliary inductor, both ZVS turn-on of the main switches and soft turn-off of the body diodes can be achieved. In the proposed totem-pole PFC topology since the switching losses and the reverse recovery losses can be significantly reduced, the typical Si MOSFETs can be employed. In addition the circulating current is reduced by adjusting the switching frequency. The proposed PFC topology can be a low cost solution to achieve high efficiency in high power PFC applications. The validity and the feasibility of the proposed topology is verified by the experimental results with a 3.3kW interleaved totem-pole PFC converter.