• Title/Summary/Keyword: Frequency Generator

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$SiO_2/Si_3N_4/SiO_2$$Si_3N_4/SiO_2/Si_3N_4$ 터널 장벽을 사용한 금속 실리사이드 나노입자 비휘발성 메모리소자의 열적 안정성에 관한 연구

  • Lee, Dong-Uk;Kim, Seon-Pil;Han, Dong-Seok;Lee, Hyo-Jun;Kim, Eun-Gyu;Yu, Hui-Uk;Jo, Won-Ju
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.02a
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    • pp.139-139
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    • 2010
  • 금속 실리사이드 나노입자는 열적 및 화학적 안정성이 뛰어나고, 절연막내에 일함수 차이에 따라 깊은 양자 우물구조가 형성되어 비휘발성 메모리 소자를 제작할 수 있다. 그러나 단일 $SiO_2$ 절연막을 사용하였을 경우 저장된 전하의 정보 저장능력 및 쓰기/지우기 시간을 향상시키는 데 물리적 두께에 따른 제한이 따른다. 본 연구에서는 터널장벽 엔지니어링을 통하여 물리적인 두께는 단일 $SiO_2$ 보다는 두꺼우나 쓰기/지우기 동작을 위하여 인가되는 전기장에 의하여 상대적으로 전자가 느끼는 상대적인 터널 절연막 두께를 감소시키는 방법으로 동작속도를 향상 시킨 $SiO_2/Si_3N_4/SiO_2$$Si_3N_4/SiO_2/Si_3N_4$ 터널 절연막을 사용한 금속 실리사이드 나노입자 비휘발성 메모리를 제조하였다. 제조방법은 우선 p-type 실리콘 웨이퍼 위에 100 nm 두께로 증착된 Poly-Si 층을 형성 한 이후 소스와 드레인 영역을 리소그래피 방법으로 형성시켜 트랜지스터의 채널을 형성한 이후 그 상부에 $SiO_2/Si_3N_4/SiO_2$ (2 nm/ 2 nm/ 3 nm) 및 $Si_3N_4/SiO_2/Si_3N_4$ (2 nm/ 3 nm/ 3 nm)를 화학적 증기 증착(chemical vapor deposition)방법으로 형성 시킨 이후, direct current magnetron sputtering 방법을 이용하여 2~5 nm 두께의 $WSi_2$$TiSi_2$ 박막을 증착하였으며, 나노입자 형성을 위하여 rapid thermal annealing(RTA) system을 이용하여 $800{\sim}1000^{\circ}C$에서 질소($N_2$) 분위기로 1~5분 동안 열처리를 하였다. 이후 radio frequency magnetron sputtering을 이용하여 $SiO_2$ control oxide layer를 30 nm로 증착한 후, RTA system을 이용하여 $900^{\circ}C$에서 30초 동안 $N_2$ 분위기에서 후 열처리를 하였다. 마지막으로 thermal evaporator system을 이용하여 Al 전극을 200 nm 증착한 이후 리소그래피와 식각 공정을 통하여 채널 폭/길이 $2{\sim}5{\mu}m$인 비휘발성 메모리 소자를 제작하였다. 제작된 비휘발성 메모리 소자는 HP 4156A semiconductor parameter analyzer와 Agilent 81101A pulse generator를 이용하여 전기적 특성을 확인 하였으며, 측정 온도를 $25^{\circ}C$, $85^{\circ}C$, $125^{\circ}C$로 변화시켜가며 제작된 비휘발성 메모리 소자의 열적 안정성에 관하여 연구하였다.

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Design of a CCM/DCM dual mode DC-DC Buck Converter with Capacitor Multiplier (커패시터 멀티플라이어를 갖는 CCM/DCM 이중모드 DC-DC 벅 컨버터의 설계)

  • Choi, Jin-Woong;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.9
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    • pp.21-26
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    • 2016
  • This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.

A Low Jitter Delay-Locked Loop for Local Clock Skew Compensation (로컬 클록 스큐 보상을 위한 낮은 지터 성능의 지연 고정 루프)

  • Jung, Chae-Young;Lee, Won-Young
    • The Journal of the Korea institute of electronic communication sciences
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    • v.14 no.2
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    • pp.309-316
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    • 2019
  • In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

Turbine Efficiency Measurement of Pulsating Flow in a Twin Scroll Turbocharger (맥동 유동이 있는 트윈 스크롤 터보과급기의 터빈 효율 측정)

  • Chung, Jin-Eun;Jeon, Se-Hun
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.22 no.2
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    • pp.386-391
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    • 2021
  • Turbocharging is becoming a key technology for both diesel and gasoline engines. Regarding gasoline engines, turbocharging can help reduce carbon dioxide (CO2) emissions when used in conjunction with other technologies. This paper presents measurements of the turbine efficiency of pulsating flow in a twin-scroll turbocharger for gasoline engines. A cold gas test bench with a pulse generator was manufactured. The turbine efficiencies were calculated using the measured data of the instantaneous pressure and temperature of the inlet and exit of the turbine. The measurements were carried out at turbine speeds from 60,000 to 100,000 rpm under a pulsating flow of 25.0 Hz and 33.0 Hz. The turbine efficiencies ranged from 0.517 to 0.544. At the pulse frequency, 33.3 Hz, the variations in efficiency were 7.7% and 2.6% at turbine speeds of 60,000 rpm and 100,000 rpm, respectively. The turbine efficiency of the pulsating flow compared to those of steady flow was 7.0% and 3.0% lower at a turbine speed of 60,000 rpm and 100,000 rpm, respectively. The pulsating flow deteriorated the turbine efficiency, but the effects of pulsating flow decreased with increasing turbine speed.

Method of the Laboratory Wave Generation for Two Dimensional Hydraulic Model Experiment in the Coastal Engineering Fields: Case of Random Waves (해안공학분야에서 2차원 수리모형실험을 위한 실험파 설정방법: 불규칙파 대상)

  • Lee, Jong-In;Bae, Il Rho;Kim, Young-Taek
    • Journal of Korean Society of Coastal and Ocean Engineers
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    • v.33 no.6
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    • pp.383-390
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    • 2021
  • The experiments in coastal engineering are very complex and a lot of components should be concerned. The experience has an important role in the successful execution. Hydraulic model experiments have been improved with the development of the wave generator and the advanced measuring apparatus. The hydraulic experiments have the advantage, that is, the stability of coastal structures and the hydraulic characteristics could be observed more intuitively rather than the numerical modelings. However, different experimental results can be drawn depending on the model scale, facilities, apparatus, and experimenters. In this study, two-dimensional hydraulic experiments were performed to suggest the guide of the test wave(random wave) generation, which is the most basic and important factor for the model test. The techniques for generating the random waves with frequency energy spectrum and the range for the incident wave height [(HS)M/(HS)T = 1~1.05] were suggested. The proposed guide for the test wave generation will contribute to enhancing the reliability of the experimental results in coastal engineering.

A Security SoC embedded with ECDSA Hardware Accelerator (ECDSA 하드웨어 가속기가 내장된 보안 SoC)

  • Jeong, Young-Su;Kim, Min-Ju;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.7
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    • pp.1071-1077
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    • 2022
  • A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

Development of an Automated Synthesizer for the Routine Production of Ga-68 Radiopharmaceuticals (임상용 Ga-68 표지 방사성의약품의 합성을 위한 자동합성장치 개발)

  • Jun Young PARK;Jeongmin SON;Won Jun KANG
    • Korean Journal of Clinical Laboratory Science
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    • v.55 no.4
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    • pp.253-260
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    • 2023
  • The germanium-68/gallium-68 (68Ge/68Ga) generator has high spatial utilization and requires little maintenance, making it economical and easy to produce. Thus, the frequency of use of 68Ga radiopharmaceuticals is rapidly increasing worldwide. Therefore, this study attempted to develop an automated synthesizer for the routine clinical application of 68Ga radiopharmaceuticals. The automated synthesizer was based on a fixed tubing system and the structure was designed after adjusting the position of the parts to reflect the synthesis method. Using various components that can be supplied in Korea, the automated synthesizer was manufactured at a much lower price cost than that of a commercialized automated synthesizer sold by companies. 68Ga-DOTA-[Tyr3]-octreotide (68Ga-DOTATOC) was synthesized to evaluate the performance of the automated synthesizer. 68Ga-DOTATOC could be synthesized with about 65% of non-decay corrected yield, and the synthesized 68Ga-DOTATOC met all quality control standards. We have synthesized 68Ga-DOTATOC more than 100 times, and only faced a few problems caused by mechanical errors. In this study, we successfully developed a simple automated synthesizer for 68Ga radiopharmaceuticals with high reproducibility. As various 68Ga radiopharmaceuticals have recently been developed, it is expected that the automated synthesizer developed in this study will be useful for routine clinical use.

An Efficient CT Image Denoising using WT-GAN Model

  • Hae Chan Jeong;Dong Hoon Lim
    • Journal of the Korea Society of Computer and Information
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    • v.29 no.5
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    • pp.21-29
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    • 2024
  • Reducing the radiation dose during CT scanning can lower the risk of radiation exposure, but not only does the image resolution significantly deteriorate, but the effectiveness of diagnosis is reduced due to the generation of noise. Therefore, noise removal from CT images is a very important and essential processing process in the image restoration. Until now, there are limitations in removing only the noise by separating the noise and the original signal in the image area. In this paper, we aim to effectively remove noise from CT images using the wavelet transform-based GAN model, that is, the WT-GAN model in the frequency domain. The GAN model used here generates images with noise removed through a U-Net structured generator and a PatchGAN structured discriminator. To evaluate the performance of the WT-GAN model proposed in this paper, experiments were conducted on CT images damaged by various noises, namely Gaussian noise, Poisson noise, and speckle noise. As a result of the performance experiment, the WT-GAN model is better than the traditional filter, that is, the BM3D filter, as well as the existing deep learning models, such as DnCNN, CDAE model, and U-Net GAN model, in qualitative and quantitative measures, that is, PSNR (Peak Signal-to-Noise Ratio) and SSIM (Structural Similarity Index Measure) showed excellent results.

A development of DS/CDMA MODEM architecture and its implementation (DS/CDMA 모뎀 구조와 ASIC Chip Set 개발)

  • 김제우;박종현;김석중;심복태;이홍직
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.6
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    • pp.1210-1230
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    • 1997
  • In this paper, we suggest an architecture of DS/CDMA tranceiver composed of one pilot channel used as reference and multiple traffic channels. The pilot channel-an unmodulated PN code-is used as the reference signal for synchronization of PN code and data demondulation. The coherent demodulation architecture is also exploited for the reverse link as well as for the forward link. Here are the characteristics of the suggested DS/CDMA system. First, we suggest an interlaced quadrature spreading(IQS) method. In this method, the PN coe for I-phase 1st channel is used for Q-phase 2nd channels and the PN code for Q-phase 1st channel is used for I-phase 2nd channel, and so on-which is quite different from the eisting spreading schemes of DS/CDMA systems, such as IS-95 digital CDMA cellular or W-CDMA for PCS. By doing IQS spreading, we can drastically reduce the zero crossing rate of the RF signals. Second, we introduce an adaptive threshold setting for the synchronization of PN code, an initial acquistion method that uses a single PN code generator and reduces the acquistion time by a half compared the existing ones, and exploit the state machines to reduce the reacquistion time Third, various kinds of functions, such as automatic frequency control(AFC), automatic level control(ALC), bit-error-rate(BER) estimator, and spectral shaping for reducing the adjacent channel interference, are introduced to improve the system performance. Fourth, we designed and implemented the DS/CDMA MODEM to be used for variable transmission rate applications-from 16Kbps to 1.024Mbps. We developed and confirmed the DS/CDMA MODEM architecture through mathematical analysis and various kind of simulations. The ASIC design was done using VHDL coding and synthesis. To cope with several different kinds of applications, we developed transmitter and receiver ASICs separately. While a single transmitter or receiver ASC contains three channels (one for the pilot and the others for the traffic channels), by combining several transmitter ASICs, we can expand the number of channels up to 64. The ASICs are now under use for implementing a line-of-sight (LOS) radio equipment.

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Research on the Actual Condition of the radiation Safety Management(RSM) for the Educated Training of the Dental Diagnostics X-ray Generators (교육용 치과 엑스선 발생장치에 대한 방사선 안전 관리 실태 조사)

  • Lee, Mihyeon;Yu, Yunsik;Lee, Jaeseung;Im, Inchul
    • Journal of the Korean Society of Radiology
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    • v.8 no.7
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    • pp.467-477
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    • 2014
  • The purpose of this study is to offer data base for establishment of dental training x-ray generator based safety usage through surveying real radiation safety management state of radiation worker's in plan of operations that have dental training x-ray generators and use it. For it, comprehensive references were surveyed referring reports of current state of regulation technique development and domestic radiation safety evaluation and nuclear related legislation regarding radiation safety management of dental training x-ray generators. On the basis of it, questionnaires were filled in about respondent's general characteristic radiation safety manager's status current state of radiation safety management and the level of knowledge & consciousness. For the study, the survey was conducted to 224 people of radiation safety managers and university graduates training assistants and full-time professors who can treat dental training x-ray generators in education center. through this survey 95 questionnaires were used as analysis materials except the insufficient and omitted responses. As a method of analysis, the frequency and percentage were figured out with the general characteristics and safety manager's status. Chi-square test for frequency and correlation per question analysis and Pearson correlation analysis for crosslevel correlation were done with current state of radiation safety management and knowledge & consciousness level. As a result, running dental training x-ray generators was dealt with by 20's to 40's who have high education level over post undergraduate degree and major in dental hygienic. In addition, female have higher consciousness level for radiation safety management than male. It shows significal linear relation statistically(${\chi}^2$ >5, 0.1${\chi}^2$ >5, 0.3${\chi}^2$ >5, 0.3