• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.5
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• pp.3079-3085
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• 2014

This paper suggests a power level controllable frequency up-converter which is designed and fabricated using both the filtering technology consisted with only passive devices and a multi-level digital attenuator. The suggested frequency up-converter simultaneously realizes the low power consumption and the low cost model. Because of the possibility for controlling power levels, it is possible to use the suggested frequency up-converter for wide spectral range. According to the experimental results, the average gain value of 0.75dB is obtained for the bandwidth of 160MHz at the center frequency of 1,200MHz. Especially, it is confirmed that the power level can be controlled from 10 to -21.5dBm through the digital attenuator.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.891-896
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• 2011

This paper describes the differential voltage-to-frequency converter which is realized current conveyor circuits. The output frequency of the differential voltage-to-frequency converter is proportional to the difference of two input voltages. The designed circuit is simulated by HSPICE. The range of input voltage difference is from several volts to several milli-volts. From the simulation results the error is less than from -1.9% to +1.8% compared to the calculated values.

• Publications of The Korean Astronomical Society
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• v.22 no.3
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• pp.83-87
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• 2007

We designed the Intermediate Frequency(IF) distributor for multi beam backend system and manufactured Voltage to Frequency Converter(VFC) to measure the multi-beam receiver performance. Multi beam receiver has 15 channel receivers and can get 15 spectrums at once. The multi beam receiver has more observation efficiency than single beam receiver. We manufactured the 15 IF distributors to distribute IF signal for Autocorrelation spectrometer that is radio signal processor. Also, we manufactured the VF Converter to test the performance measurement of receiver for Korea VLBI Network(KVN) system which is under-construct in Seoul, Ulsan and Jeju. As a result of performance measurement, we could obtain linearity of 99.4% on the input power vs output frequency and measured the operating range of input frequency.

• Journal of the Korean Society of Safety
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• v.3 no.1
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• pp.21-29
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• 1988

Conventional pwm switching power supply have the disadvantage some aspects of size, light weight, noise and system stability. High frequency Series Resonant Converter (SRC), described in this paper, almost improve above disadvantages. We use the state plane technique as analysis method. This technique is powerful tool which can clearly analyze the peak stress of the state variables inside the converter, Here, we can define each operation mode from frequency ratio Fsn, switching frequency to resonant frequency, and we analyze the output performance in each operation mode. To verify the theoretical analysis, we compose the actual converter, and the experimental results are compared with analysis.

• Journal of Power Electronics
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• v.9 no.1
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• pp.36-42
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• 2009

This paper presents a review of an improved high power-high frequency III-V wide bandgap (WBG) semiconductor device, Gallium Nitride (GaN). The device offers better efficiency and thermal management with higher switching frequency. By having higher blocking voltage, GaN can be used for high voltage applications. In addition, the weight and size of passive components on the printed circuit board can be reduced substantially when operating at high frequency. With proper management of thermal and gate drive design, the GaN power converter is expected to generate higher power density with lower stress compared to its counterparts, Silicon (Si) devices. The main contribution of this work is to provide additional information to young researchers in exploring new approaches based on the device's capability and characteristics in applications using the GaN power converter design.

• Journal of Power Electronics
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• v.14 no.3
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• pp.598-607
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• 2014

This paper proposes a frequency-locked loop (FLL) scheme for a single-phase grid-connected converter. A second-order generalized integrator (SOGI) based on fuzzy logic (FL) is applied to this converter to achieve precise phase angle detection. The use of this method enables the compensation of the nonlinear characteristic of the frequency error, which is defined in the SOGI scheme as the variation of the central frequency through the self-tuning gain. With the proposed scheme, the performance of the SOGI-FLL is further improved at the grid disturbances, which results in the stable operation of the grid converter under grid voltage sags or frequency variation. The PSIM simulation and experimental results are shown to verify the effectiveness of the proposed method.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.8
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• pp.423-429
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• 2006

Recently, the high frequency isolated boost DC/DC converter has been widely used for the PCS (Power Conditioning System) system because of its small size and low cost. However, the high frequency isolated boost DC/DC converters applied the conventional voltage-fed converter and current-fed converter have the problems such as the high conduction losses and the surge voltage due to the high circulating current and the leakage inductance, respectively. To overcome this problems, in this paper the secondary LLC resonant converter is proposed, and the experimental results of the secondary LLC series resonant converter for boost DC/DC converter are verified on the simulation based on the theoretical analysis and the 700W experimental prototype.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.5
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• pp.371-378
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• 2015

In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent.current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent.current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator's efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.

• KEPCO Journal on Electric Power and Energy
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• v.6 no.4
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• pp.473-480
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• 2020

In this paper, we proposed a high frequency equivalent circuit considering parasitic impedance components for differential noise analysis on the input stage during DC-DC buck converter switching operation. Based on the proposed equivalent circuit model, we presented a method to measure parasitic impedance parameters included in DC bus plate, IGBT, and PCB track using the gain phase method of a network analyzer. In order to verify the validity of this model, a DC-DC prototype consisting of a buck converter, a signal analyzer, and a LISN device, and then resonance frequency was measured in the frequency range between 150 kHz and 30 MHz. The validity of the parasitic impedance measurement method and the proposed equivalent model is verified by deriving that the measured resonance frequency and the resonance frequency of the proposed high frequency equivalent model are the same.